1
®
FN8218.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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X98017
170MHz Triple Video Digitizer with
Digital PLL
The X98017 3-channel, 8-bit Analog Front End (AFE)
contains all the components necessary to digitize analog
RGB or YUV graphics signals from personal computers,
workstations and video set-top boxes. The fully differential
analog design provides high PSRR and dynamic
performance to meet the stringent requirements of the
graphics display industry. The AFE’s 170MSPS conversion
rate supports resolutions up to UXGA at 60Hz refresh rate,
while the front end's high input bandwidth ensures sharp
images at the highest resolutions.
To minimize noise, the X98017's analog section features 2
sets of pseudo-differential RGB inputs with programmable
input bandwidth, as well as internal DC restore clamping
(including mid-scale clamping for YUV signals). This is
followed by the programmable gain/offset stage and the
three 170MSPS Analog-to-Digital Converters (ADCs).
Automatic Black Level Compensation (ABLC™) eliminates
part-to-part offset variation, ensuring perfect black level
performance in every application.
The X98017's digital PLL generates a pixel clock from the
analog source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 170MHz
with sampling clock jitter of 250ps peak to peak.
Features
170MSPS maximum conversion rate
Low PLL clock jitter (250ps p-p @ 170MSPS)
64 interpixel sampling positions
0.35V
p-p
to 1.4V
p-p
video input range
Programmable bandwidth (100MHz to 780MHz)
2 channel input multiplexer
RGB and YUV 4:2:2 output formats
5 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
Completely independent 8 bit gain/10 bit offset control
CSYNC and SOG support
Trilevel sync detection
1.05W typical P
D
@ 170MSPS
Pb-free plus anneal available (RoHS compliant)
Applications
LCD Monitors and Projectors
Digital TVs
Plasma Display Panels
RGB Graphics Processing
Scan Converters
Simplified Block Diagram
RGB/YPbPr
IN
1
PGA
8 bit ADC
Offset
DAC
ABLC™
8 or 16
x3
SOG
IN
1/2
HSYNC
IN
1/2
VSYNC
IN
1/2
Sync
Processing
Digital PLL
Voltage
Clamp
RGB/YPbPr
IN
2
3
3
RGB/YUV
OUT
PIXELCLK
OUT
HS
OUT
HSYNC
OUT
AFE Configuration and Control
VSYNC
OUT
+
Data Sheet March 8, 2006
N
O
T
R
E
C
O
M
M
E
N
D
E
D
F
O
R
N
E
W
D
E
S
I
G
N
S
-
T
H
E
I
S
L
9
8
0
0
1
-
1
7
0
I
S
A
1
0
0
%
C
O
M
P
A
T
I
B
L
E
I
M
P
R
O
V
E
D
A
L
T
E
R
N
A
T
I
V
E
2
FN8218.3
March 8, 2006
Block Diagram
Ordering Information
PART NUMBER PART MARKING
MAXIMUM PIXEL
RATE
TEMP RANGE
(°C) PACKAGE
X98017L128-3.3 X98017L-3.3 170MHz 0 to 70 128 MQFP
X98017L128-3.3-Z (See Note) X98017L-3.3Z 170MHz 0 to 70 128 MQFP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
G
IN
1
RGB
GND
1
G
IN
2
RGB
GND
2
V
IN
+
V
IN
-
PGA
8 bit ADC
+
V
CLAMP
R
IN
1
R
IN
2
V
IN
+
V
IN
-
PGA
8 bit ADC
+
V
CLAMP
B
IN
1
B
IN
2
V
IN
+
V
IN
-
PGA
8 bit ADC
+
V
CLAMP
Offset
DAC
Offset
DAC
Offset
DAC
ABLC™
ABLC™
ABLC™
8
10
8
10
8
10
8
B
S
[7:0]
8
B
P
[7:0]
8
G
S
[7:0]
8
G
P
[7:0]
8
R
S
[7:0]
8
R
P
[7:0]
SOG
IN
1
SOG
IN
2
HSYNC
IN
1
HSYNC
IN
2
VSYNC
IN
1
VSYNC
IN
2
CLOCKINV
XTAL
IN
XTAL
OUT
SCL
SDA
SADDR
Sync
Processing
Digital PLL
AFE Configuration
and Control
DATACLK
DATACLK
HS
OUT
VS
OUT
Serial
Interface
Output Data Formatter
HSYNC
OUT
VSYNC
OUT
XTALCLK
OUT
X98017
3
FN8218.3
March 8, 2006
T
Absolute Maximum Ratings Recommended Operating Conditions
Voltage on V
A
, V
D
, or V
X
(referenced to GND
A
=GND
D
=GND
X
) . . . . . . . . . . . . . . . . . . . 4.0V
Voltage on any analog input
pin
(referenced to GND
A
) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
A
Voltage on any digital input
pin
(referenced to GND
D
) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Current into any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20mA
Operating Temperature range . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . V
A
= V
D
= V
X
= 3.3V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Electrical Specifications Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 170MHz, f
XTAL
= 25MHz, T
A
= 25°C,
unless otherwise noted
SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT
FULL CHANNEL CHARACTERISTICS
ADC Resolution 8Bits
Missing Codes Guaranteed monotonic None
Conversion Rate Per Channel 10 170 MHz
DNL Differential Non-Linearity ±0.5 +1.0
-0.9
LSB
INL Integral Non-Linearity ±1.1 ±3.25 LSB
Gain Adjustment Range ±6 dB
Gain Adjustment Resolution 8Bits
Gain Matching Between Channels Percent of full scale ±1 %
Full Channel Offset Error, ABLC™ enabled ADC LSBs, over time and temperature ±0.125 ±0.5 LSB
Offset Adjustment Range, ABLC™
enabled or disabled
ADC LSBs (see ABLC™ applications
information section)
±127 LSB
Overvoltage Recovery Time For 150% overrange, maximum bandwidth
setting
5ns
ANALOG VIDEO INPUT CHARACTERISTICS (R
IN
1, G
IN
1, B
IN
1, R
IN
2, G
IN
2, B
IN
2)
Input Range 0.35 0.7 1.4 V
P-P
Input Bias Current DC restore clamp off ±0.01 ±1 µA
Input Capacitance 5pF
Full Power Bandwidth Programmable 780 MHz
INPUT CHARACTERISTICS (SOG
IN
1, SOG
IN
2)
V
IH
/V
IL
Input Threshold Voltage Programmable - See Register Listing for
Details
0 to
-0.3
V
Hysteresis Centered around threshold voltage 40 mV
Input capacitance 5pF
INPUT CHARACTERISTICS (HSYNC
IN
1, HSYNC
IN
2)
V
IH
/V
IL
Input Threshold Voltage Programmable - See Register Listing for
Details
0.4 to 3.2 V
Hysteresis Centered around threshold voltage 240 mV
R
IN
Input impedance 1.2 k
X98017

X98017L128-3.3-Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE 170MHZ TRPL VID DIGI W/DIGTL PLL 12 8LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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