16
FN8218.3
March 8, 2006
Offset can drift significantly over 50°C, reducing image
quality and requiring that the user do a manual calibration
once the monitor has warmed up.
In addition to drift, many AFEs exhibit interaction between
the offset and gain controls. When the gain is changed, the
magnitude of the offset is changed as well. This again
increases the complexity of the firmware as it tries to
optimize gain and offset settings for a given video input
signal. Instead of adjusting just the offset, then the gain, both
have to be adjusted interactively until the desired ADC
output is reached.
The X98017 simplifies offset and gain adjustment and
completely eliminates offset drift using its Automatic Black
Level Compensation (ABLC™) function. ABLC™ monitors
the black level and continuously adjusts the X98017's 10 bit
offset DACs to null out the offset. Any offset, whether due to
the video source or the X98017's analog amplifiers, is
eliminated with 10 bit (1/4 of an 8 bit ADC LSB) accuracy.
Any drift is compensated for well before it can have a visible
effect. Manual offset adjustment control is still available - an
8 bit register allows the firmware to adjust the offset ±64
codes in exactly 1 ADC LSB increments. And gain is now
completely independent of offset - adjusting the gain no
longer affects the offset, so there is no longer a need to
program the firmware to cope with interactive offset and gain
controls.
Finally, there should be no concerns over ABLC™ itself
introducing visible artifacts; it doesn't. ABLC™ operates at a
very low frequency, changing the offset in 1/4 LSB
increments, so it doesn't cause visible brightness
fluctuations. And once ABLC™ is locked, if the offset doesn't
drift, the DACs won't change. If desired, ABLC™ can be
disabled, allowing the firmware to work in the traditional way,
with 10 bit offset DACs under the firmware's control.
Gain and Offset Control
To simplify image optimization algorithms, the X98017
features fully-independent gain and offset adjustment.
Changing the gain does not affect the DC offset, and the
weight of an Offset DAC LSB does not vary depending on
the gain setting.
The full-scale gain is set in the three 8-bit registers (0x06-
0x08). The X98017 can accept input signals with amplitudes
ranging from 0.35V
P-P
to 1.4V
P-P
.
The offset controls shift the entire RGB input range,
changing the input image brightness. Three separate
registers provide independent control of the R, G, and B
channels. Their nominal setting is 0x80, which forces the
ADC to output code 0x00 (or 0x80 for U and V channels in
YUV mode) during the back porch period when ABLC™ is
enabled.
Functional Description
Inputs
The X98017 digitizes analog video inputs in both RGB and
Component (YPbPr) formats, with or without embedded sync
(SOG).
RGB Inputs
For RGB inputs, the black/blank levels are identical and
equal to 0V. The range for each color is typically 0V to 0.7V
from black to white. HSYNC and VSYNC are separate
signals.
Component YUV Inputs
In addition to RGB and RGB with SOG, the X98017 has an
option that is compatible with the component YPbPr and
YCbCr video inputs typically generated by DVD players.
While the X98017 digitizes signals in these color spaces, it
does not perform color space conversion; if it digitizes an
RGB signal, it outputs digital RGB, while if it digitizes a
YPbPr signal, it outputs digital YPbPr. For simplicity’s sake
we will call these non-RGB signals YUV.
The Luminance (Y) signal is applied to the Green Channel
and is processed in a manner identical to the Green input
with SOG described previously. The color difference signals
U and V are bipolar and swing both above and below the
black level. When the YUV mode is enabled, the black level
output for the color difference channels shifts to a mid scale
value of 0x80. Setting configuration register 0x05[2] = 1
enables the YUV signal processing mode of operation.
The X98017 can optionally decimate the incoming data to
provide a 4:2:2 output stream (configuration register
0x18[4] = 1) as shown in Table 2.
TABLE 1. YUV MAPPING (4:4:4)
INPUT
SIGNAL
X98017
INPUT
CHANNEL
X98017
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y Green Green Y
0
Y
1
Y
2
Y
3
U Blue Blue U
0
U
1
U
2
U
3
VRedRedV
0
V
1
V
2
V
3
TABLE 2. YUV MAPPING (4:2:2)
INPUT
SIGNAL
X98017
INPUT
CHANNEL
X98017
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y Green Green Y
0
Y
1
Y
2
Y
3
U Blue Blue driven low
VRedRedU
0
V
1
U
2
V
3
X98017
17
FN8218.3
March 8, 2006
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled
(see register 0x05[1]). AC coupling is usually preferred since
it allows video signals with substantial DC offsets to be
accurately digitized. The X98017 provides a complete
internal DC-restore function, including the DC restore clamp
(See Figure 7) and programmable clamp timing (registers
0x14, 0x15, 0x16, and 0x23).
When AC-coupled, the DC restore clamp is applied every
line, a programmable number of pixels after the trailing edge
of HSYNC. If register 0x05[5] = 0 (the default), the clamp will
not be applied while the DPLL is coasting, preventing any
clamp voltage errors from composite sync edges,
equalization pulses, or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC
Restore and ABLC™ Starting Pixel registers (0x14 and
0x15) has been reached. The clamp is applied for the
number of pixels specified by the DC Restore Clamp Width
Register (0x16). The clamp can be applied to the back porch
of the video, or to the front porch (by increasing the DC
Restore and ABLC™ Starting Pixel registers so all the active
video pixels are skipped).
If DC-coupled operation is desired, the input to the ADC will
be the difference between the input signal (R
IN
1, for
example) and that channel’s ground reference (RGB
GND
1 in
that example).
SOG
For component YUV signals, the sync signal is embedded
on the Y channel’s video, which is connected to the green
input, hence the name SOG (Sync on Green). The horizontal
sync information is encoded onto the video input by adding
the sync tip during the blanking interval. The sync tip level is
typically 0.3V below the video black level.
To minimize the loading on the green channel, the SOG
input for each of the green channels should be AC-coupled
to the X98017 through a series combination of a 10nF
capacitor and a 500 resistor. Inside the X98017, a window
comparator compares the SOG signal with an internal 4 bit
programmable threshold level reference ranging from 0mV
to 300mV below the minimum sync level. The SOG
threshold level, hysteresis, and low-pass filter is
programmed via register 0x04. If the Sync-On-Green
function is not needed, the SOG
IN
pin(s) may be left
unconnected.
R(GB)
IN
1
V
CLAMP
V
IN
+
V
IN
DC Restore
Clamp DAC
VGA1
CLAMP
GENERATION
DC Restoration
Automatic Black Level
Compensation (ABLC™) Loop
Bandwidth
Control
Offset
Control
Registers
8 bit ADC
Offset
ADC
To Output
Formatter
Fixed
Offset
Fixed
Offset
0x00
ABLC™
ABLC™
ABLC™
10
10
10
8
8
8
88
PGA
To
ABLC
Block
Input
Bandwidth
VGA2
R(GB)
GND
1
R(GB)
IN
2
R(GB)
GND
2
FIGURE 7. VIDEO FLOW (INCLUDING ABLC™)
X98017
18
FN8218.3
March 8, 2006
SYNC Processing
The X98017 can process sync signals from 3 different
sources: discrete HSYNC and VSYNC, composite sync on
the HSYNC input, or composite sync from a Sync-On-Green
(SOG) signal embedded on the Green video input. The
X98017 has SYNC activity detect functions to help the
firmware determine which sync source is available.
PGA
The X98017’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is:
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1 V/V for GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per
line. In normal operation this means that there is a maximum
delay of one HSYNC period between a write to a Gain
register for a particular color and the corresponding change
in that channel’s actual PGA gain. If there is no regular
HSYNC/SOG source, or if the external clamp option is
enabled (register 0x13[5:4]) but there is no external clamp
signal being generated, it may take up to 100ms for a write
to the Gain register to update the PGA. This is not an issue
in normal operation with RGB and YUV signals.
Bandwidth and Peaking Control
Register 0x0D[3:1] controls a low pass filter allowing the
input bandwidth to be adjusted with three bit resolution
between its default value (0x0E = 780MHz) and its minimum
bandwidth (0x00, for 100MHz). Typically the higher the
resolution, the higher the desired input bandwidth. To
minimize noise, video signals should be digitized with the
minimum bandwidth setting that passes sharp edges.
0:
VGA1
0x05[0]
1:
VGA2
HSYNC
IN
1
HSYNC1
SLICER
0x03[2:0]
VSYNC
IN
1
SOG
IN
1
HSYNC2
SLICER
0x03[6:4]
HSYNC
IN
VSYNC
IN
ACTIVITY 0x01[6:0]
&
POLARITY 0x02[5:0]
DETECT
HSYNC
IN
2
VSYNC
IN
2
SOG
IN
2
SYNC
SPLITTER
PLL
0x0E through 0x13
HSYNC
OUT
VSYNC
OUT
COAST
GENERATION
0x11, 0x12, 0x13[2]
XTAL
IN
XTAL
OUT
0: ÷1
0x13
[6]
1: ÷2
÷2
XTALCLOCK
OUT
Output
Formatter
0x18,
0x19,
0x1A
Pixel Data
from AFE
24
R
P
[7:0]
R
S
[7:0]
G
P
[7:0]
G
S
[7:0]
B
P
[7:0]
B
S
[7:0]
DATACLK
HS
OUT
VS
OUT
SOG
IN
SOG
SLICER
0x1C
SOG
SLICER
0x1C
00, 10,
11:
HSYNC
IN
0x05[4:3]
01:
SOG
IN
1:
SYNC
SPLTR
0x05[3]
0:
VSYNC
IN
CLOCKINV
IN
HS
PIXCLK
CSYNC
SOURCE
SYNC
TYPE
VSYNC
DATACLK
FIGURE 8. SYNC FLOW
Gain
V
V
----


0.5
GainCode
170
-----------------------------+=
X98017

X98017L128-3.3-Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE 170MHZ TRPL VID DIGI W/DIGTL PLL 12 8LD
Lifecycle:
New from this manufacturer.
Delivery:
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