4
FN8218.3
March 8, 2006
Input capacitance 5pF
DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINV
IN
, RESET)
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
I Input leakage current RESET
has a 70k pullup to V
D
±10 nA
Input capacitance 5pF
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC
IN
1, VSYNC
IN
2)
V
T
+ Low to High Threshold Voltage 1.45 V
V
T
- High to Low Threshold Voltage 0.95 V
I Input leakage current ±10 nA
Input capacitance 5pF
DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK
)
V
OH
Output HIGH Voltage, I
O
= 16mA 2.4 V
V
OL
Output LOW Voltage, I
O
= -16mA 0.4 V
DIGITAL OUTPUT CHARACTERISTICS (R
P
, G
P
, B
P
, R
S
, G
S
, B
S
, HS
OUT
, VS
OUT
, HSYNC
OUT
, VSYNC
OUT
)
V
OH
Output HIGH Voltage, I
O
= 8mA 2.4 V
V
OL
Output LOW Voltage, I
O
= -8mA 0.4 V
R
TRI
Pulldown to GND
D
when three-state R
P
, G
P
, B
P
, R
S
, G
S
, B
S
only 58 k
DIGITAL OUTPUT CHARACTERISTICS (SDA, XTALCLK
OUT
)
V
OH
Output HIGH Voltage, I
O
= 4mA XTALCLK
OUT
only; SDA is open-drain 2.4 V
V
OL
Output LOW Voltage, I
O
= -4mA 0.4 V
POWER SUPPLY REQUIREMENTS
V
A
Analog Supply Voltage 3 3.3 3.6 V
V
D
Digital Supply Voltage 3 3.3 3.6 V
V
X
Crystal Oscillator Supply Voltage 3 3.3 3.6 V
I
A
Analog Supply Current Operating 185 195 mA
I
D
Digital Supply Current Operating (grayscale) 135 145 mA
I
X
Crystal Oscillator Supply Current 0.7 2 mA
P
D
Total Power Dissipation Operating (average) 1.05 1.25 W
Power-down Mode 50 80 mW
Θ
JA
Thermal Resistance, Junction to Ambient 30 °C/W
AC TIMING CHARACTERISTICS
PLL Jitter 250 450 ps p-p
Sampling Phase Steps 5.6° per step 64
Sampling Phase Tempco ±1 ps/°C
Sampling Phase Differential Nonlinearity Degrees out of 360° ±3 °
HSYNC Frequency Range 10 150 kHz
f
XTAL
Crystal Frequency Range 23 25 27 MHz
Electrical Specifications Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 170MHz, f
XTAL
= 25MHz, T
A
= 25°C,
unless otherwise noted (Continued)
SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT
X98017
5
FN8218.3
March 8, 2006
t
SETUP
DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
1.3 ns
t
HOLD
DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
2.0 ns
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
f
SCL
SCL Clock Frequency 0 400 kHz
Maximum width of a glitch on SCL that will
be suppressed
2 XTAL periods min 80 ns
t
AA
SCL LOW to SDA Data Out Valid 5 XTAL periods plus SDA’s RC time
constant
See
comment
µs
t
BUF
Time the bus must be free before a new
transmission can start
1.3 µs
t
LOW
Clock LOW Time 1.3 µs
t
HIGH
Clock HIGH Time 0.6 µs
t
SU:STA
Start Condition Setup Time 0.6 µs
t
HD:STA
Start Condition Hold Time 0.6 µs
t
SU:DAT
Data In Setup Time 100 ns
t
HD:DAT
Data In Hold Time 0ns
t
SU:STO
Stop Condition Setup Time 0.6 µs
t
DH
Data Output Hold Time 4 XTAL periods min 160 ns
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
Electrical Specifications Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 170MHz, f
XTAL
= 25MHz, T
A
= 25°C,
unless otherwise noted (Continued)
SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT
t
SU:STO
t
DH
t
HIGH
t
SU:ST
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
FIGURE 1. 2 WIRE INTERFACE TIMING
DATACLK
t
SETUP
t
HOLD
DATACLK
Pixel Data
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
X98017
6
FN8218.3
March 8, 2006
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
D
0
R
P
/G
P
/B
P
[7:0]
HS
OUT
8.5 DATACLK Pipeline Latency
R
S
/G
S
/B
S
[7:0]
P
10
P
11
P
12
D
1
D
2
D
3
HSYNC
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 3. 24 BIT OUTPUT MODE
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
8.5 DATACLK Pipeline Latency
P
10
P
11
P
12
HSYNC
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
G
0
(Y
o
) G
1
(Y
1
)G
2
(Y
2
)
B
0
(U
o
)R
1
(V
1
)B
2
(U
2
)
G
P
[7:0]
R
P
[7:0]
B
P
[7:0]
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
X98017

X98017L128-3.3-Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE 170MHZ TRPL VID DIGI W/DIGTL PLL 12 8LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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