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X98017L128-3.3-Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
7
FN8218.3
March 8, 2006
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +10.5)*t
PIXEL
D
1
D
3
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
D
0
R
P
/G
P
/B
P
[7:0]
HS
OUT
P
10
P
11
P
12
D
2
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
R
S
/G
S
/B
S
[7:0]
HSYNC
IN
The HSYNC ed
g
e
(p
ro
g
rammable leadin
g
or trailin
g)
that the DPLL is locked to.
HSYNC
FIGURE 5. 48 BIT OUTPUT MODE
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
P
10
P
11
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
HSYNC
IN
D
0
R
P
/G
P
/B
P
[7:0] D
2
D
1
R
S
/G
S
/B
S
[7:0]
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
X98017
8
FN8218.3
March 8, 2006
Pinout
X98017
(128-PIN MQFP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
NC
NC
GND
A
V
BYPASS
GND
A
V
A
R
IN
1
GND
A
V
BYPASS
GND
A
V
A
G
IN
1
RGB
GND
1
SOG
IN
1
GND
A
V
BYPASS
GND
A
V
A
B
IN
1
V
A
GND
A
R
IN
2
GND
A
G
IN
2
RGB
GND
2
SOG
IN
2
GND
A
B
IN
2
V
A
GND
A
V
COREADC
GND
D
HS Y NC
IN
1
HS Y NC
IN
2
V
A
GND
A
GND
X
V
X
R
S
5
R
S
6
R
S
7
V
D
GND
D
G
P
0
G
P
1
G
P
2
G
P
3
G
P
4
G
P
5
G
P
6
G
P
7
V
D
GND
D
G
S
0
G
S
1
G
S
2
G
S
3
G
S
4
G
S
5
G
S
6
G
S
7
V
CORE
GND
D
V
D
GND
D
B
P
0
B
P
1
B
P
2
B
P
3
B
P
4
B
P
5
B
P
6
B
P
7
V
D
GND
D
VR EG
IN
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
VSYNC
OUT
HS Y NC
OUT
VS
OUT
HS
OUT
V
D
GND
D
DAT AC L K
DAT AC L K
GND
D
R
P
0
R
P
1
R
P
2
R
P
3
R
P
4
R
P
5
R
P
6
R
P
7
V
D
GND
D
V
CORE
GND
D
R
S
0
R
S
1
R
S
2
R
S
3
R
S
4
XTAL
IN
XTAL
OUT
CLOCKINV
IN
V
PLL
GND
D
VSYNC
IN
1
VSYNC
IN
2
RESET
XTALCLOCK
OUT
S ADDR
SDA
SCL
GND
D
V
CORE
GND
D
V
D
B
S
7
B
S
6
B
S
5
B
S
4
B
S
3
B
S
2
B
S
1
B
S
0
NC
VR EG
OUT
X98017
9
FN8218.3
March 8, 2006
Pin Descriptions
SYMBOL PIN DESCRIPTION
R
IN
1 7 Analog input. Red channel 1. DC couple or AC couple through 0.1µF.
G
IN
1 12 Analog input. Green channel 1. DC couple or AC couple through 0.1µF.
B
IN
1 19 Analog input. Blue channel 1. DC couple or AC couple through 0.1µF.
RGB
GND
1 13 Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
1 14 Analog input. Sync on Green. Connect to G
IN
1 through a 0.01µF capacitor in series with a 500Ω resistor.
HSYNC
IN
1 33 Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND
A
. Connect to channel 1's HSYNC
signal through a 680Ω series resistor.
VSYNC
IN
1 44 Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.
R
IN
2 22 Analog input. Red channel 2. DC couple or AC couple through 0.1µF.
G
IN
2 24 Analog input. Green channel 2. DC couple or AC couple through 0.1µF.
B
IN
2 28 Analog input. Blue channel 2. DC couple or AC couple through 0.1µF.
RGB
GND
2 25 Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
2 26 Analog input. Sync on Green. Connect to G
IN
1 through a 0.01µF capacitor in series with a 500Ω resistor.
HSYNC
IN
2 34 Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND
A
. Connect to channel 2's HSYNC
signal through a 680Ω series resistor.
VSYNC
IN
2 45 Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.
CLOCKINV
IN
41 Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame
rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to
D
GND
if unused.
RESET
46 Digital input, 5V tolerant, active low, 70kΩ pull-up to V
D
. Take low for at least 1µs and then high again to
reset the X98017. This pin is not necessary for normal use and may be tied directly to the V
D
supply.
XTAL
IN
39 Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XTAL
OUT
40 Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XTALCLK
OUT
47 3.3V digital output. Buffered crystal clock output at f
XTAL
or f
XTAL
/2. May be used as system clock for other
system components.
SADDR 48 Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A
including R/W bit) when tied high.
SCL 50 Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA 49 Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
R
P
[7:0] 112-119 3.3V digital output. Red channel, primary pixel data. 58K pulldown when three-stated.
R
S
[7:0] 100-107 3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated.
G
P
[7:0] 90-97 3.3V digital output. Green channel, primary pixel data. 58K pulldown when three-stated.
G
S
[7:0] 80-87 3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated.
B
P
[7:0] 68-75 3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated.
B
S
[7:0] 55-62 3.3V digital output. Blue channel, secondary pixel data. 58K pulldown when three-stated.
DATACLK 121 3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 48
bit mode.
DATACLK
122 3.3V digital output. Inverse of DATACLK.
X98017
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

X98017L128-3.3-Z

Mfr. #:
Buy X98017L128-3.3-Z
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE 170MHZ TRPL VID DIGI W/DIGTL PLL 12 8LD
Lifecycle:
New from this manufacturer.
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