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X98017L128-3.3-Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
10
FN8218.3
March 8, 2006
HS
OUT
125 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals)
VS
OUT
126 3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after
the trailing edge of HS
OUT
. This signal is usually not needed - use VSYNC
OUT
as VSYNC source.
HSYNC
OUT
127 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC
period. HS
OUT
should be used to detect the beginning of a line. This output will pass composite sync signals
and Macrovision signals if present on HSYNC
IN
or SOG
IN
.
VSYNC
OUT
128 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a
frame and measure the VSYNC period.
V
A
6, 11, 18, 20,
29, 35
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND
A
with 0.1µF.
GND
A
3, 5, 8, 10, 15,
17, 21, 23, 27,
30, 36
Ground return for V
A
and V
BYPASS
.
V
D
54, 67, 77, 89,
99, 111, 124
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND
D
with 0.1µF.
GND
D
32, 43, 51, 53,
66, 76, 78, 88,
98, 108, 110,
120, 123
Ground return for V
D
, V
CORE
, V
COREADC
, and V
PLL
.
V
X
38 Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND
X
with 0.1µF.
GND
X
37 Ground return for V
X
.
V
BYPASS
4, 9, 16 Bypass these pins to GND
A
with 0.1µF. Do not connect these pins to each other or anything else.
VREG
IN
65 3.3V input voltage for V
CORE
voltage regulator. Connect to a 3.3V source, and bypass to GND
D
with 0.1µF.
VREG
OUT
64 Regulated output voltage for V
PLL
, V
COREADC
and V
CORE
; typically 1.9V. Connect only to V
PLL
,
V
COREADC
and V
CORE
and bypass at input pins as instructed below. Do not connect to anything else - this
output can only supply power to V
PLL
, V
COREADC
and V
CORE
.
V
COREADC
31 Internal power for the ADC’s digital logic. Connect to VREG
OUT
through a 10Ω resistor and bypass to GND
D
with 0.1µF.
V
PLL
42 Internal power for the PLL’s digital logic. Connect to VREG
OUT
through a 10Ω resistor and bypass to GND
D
with 0.1µF.
V
CORE
52, 79, 109 Internal power for core logic. Connect to VREG
OUT
and bypass each pin to GND
D
with 0.1µF.
NC 1, 2, 63 Reserved. Do not connect anything to these pins.
Pin Descriptions (Continued)
SYMBOL PIN DESCRIPTION
X98017
11
FN8218.3
March 8, 2006
Register Listing
ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION
0x01 SYNC Status
(read only)
0 HSYNC1 Active 0: HSYNC1 is Inactive
1: HSYNC1 is Active
1 HSYNC2 Active 0: HSYNC2 is Inactive
1: HSYNC2 is Active
2 VSYNC1 Active 0: VSYNC1 is Inactive
1: VSYNC1 is Active
3 VSYNC2 Active 0: VSYNC2 is Inactive
1: VSYNC2 is Active
4 SOG1 Active 0: SOG1 is Inactive
1: SOG1 is Active
5 SOG2 Active 0: SOG2 is Inactive
1: SOG2 is Active
6 PLL Locked 0: PLL is unlocked
1: PLL is locked to incoming HSYNC
7 CSYNC Detected at
Sync Splitter Output
0: Composite Sync signal not detected
1: Composite Sync signal is detected
0x02 SYNC Polarity
(read only)
0 HSYNC1
Polarity
0: HSYNC1 is Active High
1: HSYNC1 is Active Low
1 HSYNC2
Polarity
0: HSYNC2 is Active High
1: HSYNC2 is Active Low
2VSYNC1
Polarity
0: VSYNC1 is Active High
1: VSYNC1 is Active Low
3VSYNC2
Polarity
0: VSYNC2 is Active High
1: VSYNC2 is Active Low
4 HSYNC1
Trilevel
0: HSYNC1 is Standard Sync
1: HSYNC1 is Trilevel Sync
5 HSYNC2
Trilevel
0: HSYNC2 is Standard Sync
1: HSYNC2 is Trilevel Sync
7:6 N/A Returns 0
0x03 HSYNC Slicer (0x44) 2:0 HSYNC1 Threshold 000 = lowest (0.4V) All values referred to
100 = default (2.0V) voltage at HSYNC input
111 = highest (3.2V) pin, 240mV hysteresis
3 Reserved Set to 00
6:4 HSYNC2 Threshold See HSYNC1
7 Disable Glitch Filter 0: HSYNC/VSYNC Digital Glitch Filter Enabled (default)
1: HSYNC/VSYNC Digital Glitch Filter Disabled
0x04 SOG Slicer (0x08) 3:0 SOG1 and SOG2
Threshold
0x0 = lowest (0mV) 40mV hysteresis at
0x8 = default (160mV) all settings
0xF = highest (300mV) 20mV step size
4 SOG Filter
Enable
0: SOG low pass filter disabled (default)
1: SOG low pass filter enabled, 14MHz corner
5SOG Hysteresis
Disable
0: 40mV SOG hysteresis enabled
1: 40mV SOG hysteresis disabled (default)
7:6 Reserved Set to 00.
X98017
12
FN8218.3
March 8, 2006
0x05 Input configuration (0x00) 0 Channel Select 0: VGA1
1: VGA2
1 Input Coupling 0: AC coupled (positive input connected to clamp DAC
during clamp time, negative input disconnected from outside
pad and always internally tied to appropriate clamp DAC)
1: DC coupled (+ and - inputs are brought to pads and never
connected to clamp DACs). Analog clamp signal is turned off
in this mode.
2 RGB/YUV 0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale
analog shift for R, G, and B, base ABLC™ target code = 0x00
for R, G, and B)
1: YUV inputs (Clamp DAC = 600mV for R and B, 300mV for
G, half scale analog shift for G channel only, base ABLC™
target code = 0x00 for G, = 0x80 for R and B)
3 Sync Type 0: Separate HSYNC/VSYNC
1: Composite (from SOG or CSYNC on HSYNC)
4 Composite Sync
Source
0: SOG
IN
1: HSYNC
IN
Note: If Sync Type = 0, the multiplexer will pass HSYNC
IN
regardless of the state of this bit.
5 COAST CLAMP
enable
0: DC restore clamping and ABLC™ suspended during
COAST
1: DC restore clamping and ABLC™ continue during COAST
7:6 Reserved Set to 00.
0x06 Red Gain (0x55) 7:0 Red Gain Channel gain, where:
gain (V/V) = 0.5 + [7:0]/170
0x00: gain = 0.5 V/V
(1.4VP-P input = full range of ADC)
0x55: gain = 1.0 V/V
(0.7VP-P input = full range of ADC)
0xFF: gain = 2.0 V/V
(0.35VP-P input = full range of ADC)
0x07 Green Gain (0x55) 7:0 Green Gain
0x08 Blue Gain (0x55) 7:0 Blue Gain
0x09 Red Offset (0x80) 7:0 Red Offset ABLC™ enabled: digital offset control. A 1 LSB change in
this register will shift the ADC output by 1 LSB.
ABLC™ disabled: analog offset control. These bits go to the
upper 8 bits of the 10 bit offset DAC. A 1LSB change in this
register will shift the ADC output approximately 1 LSB (Offset
DAC range = 0) or 0.5LSBs (Offset DAC range = 1).
0x00 = min DAC value or -0x80 digital offset,
0x80 = mid DAC value or 0x00 digital offset,
0xFF = max DAC value or +0x7F digital offset
0x0A Green Offset (0x80) 7:0 Green Offset
0x0B Blue Offset (0x80) 7:0 Blue Offset
0x0C Offset DAC Configuration (0x00) 0 Offset DAC Range 0: ±1/2 ADC fullscale (1 DAC LSB ~ 1 ADC LSB)
1: ±1/4 ADC fullscale (1 DAC LSB ~ 1/2 ADC LSB)
1 Reserved Set to 0.
3:2 Red Offset DAC LSBs These bits are the LSBs necessary for 10 bit manual offset
DAC control.
Combine with their respective MSBs in registers 0x09, 0x0A,
and 0x0B to achieve 10 bit offset DAC control.
5:4 Green Offset DAC
LSBs
7:6 Blue Offset DAC
LSBs
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION
X98017
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

X98017L128-3.3-Z

Mfr. #:
Buy X98017L128-3.3-Z
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE 170MHZ TRPL VID DIGI W/DIGTL PLL 12 8LD
Lifecycle:
New from this manufacturer.
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