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ADUCM322BBCZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Data Sheet ADuCM322
Rev. 0 | Page 15 of 23
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 8. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Description
A1
RESERVED
RES
No Connect. Leave this ball unconnected.
A2 RESERVED RES Connect to AGND.
A3 RESERVED RES1 Connect to AVDD_REG1.
A4 RESERVED RES1 Connect to AVDD_REG1.
A5 RESERVED RES Connect to AGND.
A6 DGND S Power Supply Ground.
A7 RESERVED RES Connect to AGND.
A8 RESERVED RES1 Connect to AVDD_REG1.
A9 RESERVED RES1 Connect to AVDD_REG1.
A10 RESERVED RES Connect to AGND.
A11 IREF AI Reference Current. This ball generates the reference current and is set by an
external resistor, R
EXT
. Connect a 3.3 kΩ R
EXT
from IREF to DGND.
B1
IOVDD1
S
3.3 V GPIO Supply.
B2
RESET
I Reset Input (Active Low). An internal pull-up resistor is included.
B3 P3.3/PRTADDR3/PLAI[15] I/O Digital Input/Output Port 3.3 (P3.3).
MDIO Port Address Bit 3 (PRTADDR3). See the Digital Inputs parameter in
Table 1 for details.
Output of PLA Element 15 (PLAI[15]).
B4
RESERVED
RES
No Connect. Leave this ball unconnected.
B5 RESERVED RES No Connect. Leave this ball unconnected.
B6 DGND S Power Supply Ground.
1
A
B
C
D
E
F
G
H
J
K
L
2 3 4 5 6 7 8 9 10 11
RESERVED RESERVED
RESERVED
IOVDD1
IOGND1
P3.3/
PRTADDR3/
PLAI[15]
P0.0/
SCLK0/
PLAI[0]
RESERVED
RESERVED RESERVED
RESERVED
RESERVED
IREF
RESERVED
DGND
DGND2
SWCLK
AIN15/
P4.7
AIN14/
P4.6
AIN12/
P4.4
AIN11/
BUF_
VREF2V5
AIN10
AIN7
AIN2
AIN1
AIN0AGND1
VDAC4
VDAC7/
P5.2
VDAC6/
P5.1
XTALI
IOVDD3
IOGND3
VDAC3/
P5.0
VDAC1 VDD1
AVDD3
AGND2
AGND3
AIN3
AIN4
AIN6
AIN5
AIN9/
P4.3
AIN8/
P4.2
VDAC0/
P5.3
VDAC2/
P3.7/
PLAO[29]
VDAC5DGND1
AGND4
AIN13/
P4.5
AVDD4
SWDIO IOGND2
IOVDD2
DGND
RESERVED
RESERVED RESERVED RESERVED
RESET
P1.0/SIN/
ECLKIN/
PLAI[4]
P1.2/
PWM0/
PLAI[6]
P1.1/SOUT/
PLACLK1/
PLAI[5]
P2.4/IRQ5/
ADCCONV/
PWM6/
PLAO[18]
P1.3/
PWM1/
PLAI[7]
P1.4/
PWM2/
SCLK1/
PLAO[10]
P1.5/
PWM3/
MISO1/
PLAO[11]
P1.6/
PWM4/
MOSI1/
PLAO[12]
P1.7/IRQ1/
PWM5/
CS1/
PLAO[13]
P2.0/IRQ2/
PWMTRIP/
PLACLK2/
PLAI[8]
P2.2/
IRQ4/POR/
CLKOUT/
PLAI[10]
P2.3/BM
P0.2/
MOSI0/
PLAI[2]
P0.5/
SDA0/
PLAO[3]
P2.6/
IRQ7/
PLAO[20]
P0.7/
SDA1/
PLAO[5]
P0.6/
SCL1/
PLAO[4]
P3.0/
PRTADDR0/
PLAI[12]
P3.1/
PRTADDR1/
PLAI[13]
P2.7/
IRQ8/
PLAO[21]
P3.5/
MCK/
PLAO[27]
XTALO
MDIO
P0.4/
SCL0/
PLAO[2]
P0.3/
IRQ0/CS0/
PLACLK0/
PLAI[3]
P0.1/
MISO0/
PLAI[1]
P3.2/
PRTADDR2/
PLAI[14]
P3.4/
PRTADDR4/
PLAO[26]
AVDD_
REG0
AVDD_
REG1
VREF_1V2
ADC_
REFP
ADC_
REFN
DVDD_
2V5
DVDD_1V8
ADuCM322
TOP VIEW
(Not to Scale)
13754-002
DIGITAL PINS
ANALOG PINS
ADuCM322 Data Sheet
Rev. 0 | Page 16 of 23
Pin No. Mnemonic Type
1
Description
B7 RESERVED RES No Connect. Leave this ball unconnected.
B8 RESERVED RES No Connect. Leave this ball unconnected.
B9 P1.0/SIN/ECLKIN/PLAI[4] I/O Digital Input/Output Port 1.0 (P1.0).
UART Input (SIN).
External Input Clock (ECLKIN).
Input to PLA Element 4 (PLAI[4]).
B10 P1.1/SOUT/PLACLK1/PLAI[5] I/O Digital Input/Output Port 1.1 (P1.1).
UART Output (SOUT).
PLA Clock 1(PLACLK1).
Input to PLA Element 5 (PLAI[5]).
B11 P1.2/PWM0/PLAI[6] I/O Digital Input/Output Port 1.2 (P1.2).
PWM Output 0 (PWM0).
Input to PLA Element 6 (PLAI[6]).
C1 IOGND1 S Ground for IOVDD1.
C2 P0.0/SCLK0/PLAI[0] I/O Digital Input/Output Port 0.0 (P0.0).
SPI0 Clock (SCLK0).
Input to PLA Element 0 (PLAI[0]).
C3 P2.3/BM I/O Digital Input/Output Port 2.3 (P2.3).
Boot Mode (BM). This ball determines the start-up sequence after every reset.
Pull-up is enabled at power-up.
C4 P2.2/IRQ4/
POR
/CLKOUT/PLAI[10] I/O Digital Input/Output Port 2.2 (P2.2).
External Interrupt 4 (IRQ4).
Reset Output (
POR
). This ball function is an output and it is the default for Ball C4.
Clock Output (CLKOUT).
Input to PLA Element 10 (PLAI[10]).
C5 P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O Digital Input/Output Port 2.0 (P2.0).
External Interrupt 2 (IRQ2).
PWM Trip (PWMTRIP).
PLA Input Clock 2 (PLACLK2).
Input to PLA Element 8 (PLAI[8]).
C6 P1.3/PWM1/PLAI[7] I/O Digital Input/Output Port 1.3 (P1.3).
PWM Output 1 (PWM1).
Input to PLA Element 7 (PLAI[7]).
C7 P1.4/PWM2/SCLK1/PLAO[10] I/O Digital Input/Output Port 1.4 (P1.4).
PWM Output 2 (PWM2).
SPI1 Clock (SCLK1).
Output of PLA Element 10 (PLAO[10]).
C8 P1.5/PWM3/MISO1/PLAO[11] I/O Digital Input/Output Port 1.5 (P1.5).
PWM Output 3 (PWM3).
SPI1 Master In, Slave Out (MISO1).
Output of PLA Element 11 (PLAO[11]).
C9 P1.6/PWM4/MOSI1/PLAO[12] I/O Digital Input/Output Port 1.6 (P1.6).
PWM Output 4 (PWM4).
SPI1 Master Out, Slave Input (MOSI1).
Output of PLA Element 12 (PLAO[12]).
C10 P1.7/IRQ1/PWM5/CS1/PLAO[13] I/O Digital Input/Output Port 1.7 (P1.7).
External Interrupt 1 (IRQ1).
PWM Output 5 (PWM5).
SPI1 Chip Select 1 (CS1). When using SPI1, configure this ball as CS1.
Output of PLA Element 13 (PLAO[13]).
Data Sheet ADuCM322
Rev. 0 | Page 17 of 23
Pin No. Mnemonic Type
1
Description
C11 P3.4/PRTADDR4/PLAO[26] I/O Digital Input/Output Port 3.4 (P3.4).
MDIO Port Address Bit 4 (PRTADDR4). See the Digital Inputs parameter in
Table 1 for details.
Output of PLA Element 26 (PLAO[26]).
D1 P0.2/MOSI0/PLAI[2] I/O Digital Input/Output Port 0.2 (P0.2).
SPI0 Master Out, Slave In (MOSI0).
Input to PLA Element 2 (PLAI[2]).
D2 P0.1/MISO0/PLAI[1] I/O Digital Input/Output Port 0.1 (P0.1).
SPI0 Master In, Slave Out (MISO0).
Input to PLA Element 1 (PLAI[1]).
D3
P3.2/PRTADDR2/PLAI[14]
I/O
Digital Input/Output Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2). See the Digital Inputs parameter in
Table 1 for details.
Input to PLA Element 14 (PLAI[14]).
D9 P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O Digital Input/Output Port 2.4 (P2.4).
External Interrupt 5 (IRQ5).
External Input to Start ADC Conversions (ADCCONV).
PWM Output 6 (PWM6).
Output of PLA Element 18 (PLAO[18]).
D10 DGND2 S Digital Ground 2. Connect to DGND1.
D11 IOVDD2 S 3.3 V GPIO Supply.
E1
P0.5/SDA0/PLAO[3]
I/O
Digital Input/Output Port 0.5 (P0.5).
I
2
C0 Serial Data (SDA0).
Output of PLA Element 3 (PLAO[3]).
E2 P0.4/SCL0/PLAO[2] I/O Digital Input/Output Port 0.4 (P0.4).
I
2
C0 Serial Clock (SCL0).
Output of PLA Element 2 (PLAO[2]).
E3 P0.3/IRQ0/CS0/PLACLK0/PLAI[3] I/O Digital Input/Output Port 0.3 (P0.3).
External Interrupt 0 (IRQ0).
SPI0 Chip Select 0 (CS0). When using SPI0, configure this ball as CS0.
PLA Clock 0 (PLACLK0).
Input to PLA Element 3 (PLAI[3]).
E9 SWCLK I Serial Wire Debug Clock.
E10 SWDIO I/O Serial Wire Bidirectional Data.
E11 IOGND2 S Ground for IOVDD2.
F1 P2.6/IRQ7/PLAO[20] I/O Digital Input/Output Port 2.6 (P2.6).
External Interrupt 7 (IRQ7).
Output of PLA Element 20 (PLAO[20]).
F2
P0.7/SDA1/PLAO[5]
I/O
Digital Input/Output Port 0.7 (P0.7).
I
2
C1 Serial Data (SDA1).
Output of PLA Element 5 (PLAO[5]).
F3 P0.6/SCL1/PLAO[4] I/O Digital Input/Output Port 0.6 (P0.6).
I
2
C1 Serial Clock (SCL1).
Output of PLA Element 4 (PLAO[4]).
F9 AVDD_REG0 AO Analog Regulator 0 Supply. A 470 nF capacitor to AGND4 must be connected
to this ball to stabilize the internal 2.5 V regulator that supplies the ADC.
F10 AVDD_REG1 AO Analog Regulator 1 Supply. Output of 2.5 V on-chip LDO regulator. A 470 nF
capacitor to AGND4 must be connected to this ball.
F11 VREF_1V2 S 1.2 V Reference. This ball cannot be used to source current externally.
Connect VREF_1V2 to AGNDx via a 470 nF capacitor.
G1 P2.7/IRQ8/PLAO[21] I/O Digital Input/Output Port 2.7 (P2.7).
External Interrupt 8 (IRQ8).
Output of PLA Element 21 (PLAO[21]).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ADUCM322BBCZ-RL

Mfr. #:
Buy ADUCM322BBCZ-RL
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3
Lifecycle:
New from this manufacturer.
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