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ADUCM322BBCZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ADuCM322 Data Sheet
Rev. 0 | Page 6 of 23
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS
Input Leakage Current
Logic 1 GPIO 1 nA V
IH
= V
DD
, pull-up resistor disabled
Logic 0 GPIO 10 nA V
IL
= 0 V, pull-up resistor disabled
PRTADDRx
Input Leakage Current 16 µA V
IN
= 0 V to 1.8 V, due to weak pull-
up resistors to 1.8 V
0.84
1.5
V
External resistor 91 kΩ ± 1% to
ground; range for CFP MSA high
1
Input Capacitance, All Balls Except
MCK, MDIO, PRTADDRx, and XTALx
10 pF
Input Capacitance
MCK, PRTADDRx 6.5 pF
MDIO 8.5 pF
Ball Capacitance
XTALI 5 pF
5
pF
LOGIC INPUTS
GPIO Input Voltage
Low V
INL
0.25 × IOVDDx V
V
INH
0.58 × IOVDDx
V
MDIO
PRTADDRx Input Voltage
Low V
INL
0.36 V
High V
INH
0.84 V
MCK, MDIO Input Voltage Setup time ≥10 ns; hold time ≥10 ns;
MCK/MDIO
Low V
INL
0.36 V
High V
INH
0.84 V
XTALI Input Voltage
Low V
INL
1.1 V
High V
INH
1.7 V
Pull-Up Current 30 120 µA V
IN
= 0 V, see Figure 10
30
100
µA
V
IN
= 3.3 V, see Figure 10
LOGIC OUTPUTS All digital outputs excluding XTALO
GPIO Output Voltage
6
High V
OH
IOVDDx − 0.4 V I
SOURCE
= 2 mA
Low V
OL
0.4 V I
SINK
= 2 mA
GPIO Short-Circuit Current
1
11 mA See Figure 11
MDIO
Output Voltage
High V
OH
1.0 V I
SOURCE
= 4 mA
Low V
OL
0.2 V I
SINK
= 4 mA
Delay Time 100 ns MCK to MDIO out
OSCILLATORS
Internal System Oscillator 16 MHz
Accuracy ±0.5 ±3 %
System PLL 80 MHz Main system clock
External Crystal Oscillator 16 MHz Can be selected in place of the
internal oscillator
32.768
kHz
Use for watchdog
Accuracy ±5 ±20 %
External Clock 0.05 80 MHz Can be selected in place of PLL
START-UP TIME Processor clock = 80 MHz
At Power-On 40 ms POR to first user code execution
After Other Reset 1.5 ms Reset to first user code execution
From All Power-Down Modes 1.25 µs
Data Sheet ADuCM322
Rev. 0 | Page 7 of 23
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
PROGRAMMABLE LOGIC ARRAY PLA
Propagation Delay
Ball 17 ns From input ball to output ball
Element 1.5 ns Per PLA cell
EXTERNAL INTERRUPTS
Pulse Width
1
Level Triggered
7
ns
Edge Triggered 1 ns
POWER REQUIREMENTS
7
Power Supply Voltage Range
AVDDx to AGNDx and IOVDDx
to DGNDx
1
2.9 3.3 3.6 V
Analog Power Supply Currents
AVDDx Current 4.9 mA Analog peripherals in idle mode
Digital Power Supply Current
IOVDDx Current in Normal Mode
2.7
mA
All GPIO pull-up resistors enabled
VDDx Current
Normal Mode 29 mA Clock divider (CD) = 0 (80 MHz
clock), executing typical code
20 mA CD = 1, executing typical code
10
mA
CD = 7, executing typical code
CORE_SLEEP Mode 16 mA
SYS_SLEEP Mode 8 mA
Hibernate Mode 4 mA
Additional Power Supply Currents
ADC 4.1 mA Continuously converting at
100 kSPS
DAC 340 µA Per powered up DAC, excluding
load current
Total Supply Current 37 mA VDD1, IOVDDx, AVDDx connected
together; condition when entering
user code: peripheral clocks on,
peripherals idle, no load currents
Thermal Performance
Impedance Junction to Ambient 45 °C/W JEDEC 2S2P
1
These specifications are not production tested but are guaranteed by design and/or characterization data at production release.
2
The data in this section also applies for a load of R
L
=1 kΩ and C
L
= 100 pF but only an output range of 0 V to 2.5 V.However, this specification is not production tested.
3
DAC linearity is calculated using a reduced code range of 100 to 3900.
4
DAC gain error is calculated using a reduced code range of 100 to an internal 2.5 V V
REF
.
5
Due to self heating, internal temperature measurements cannot be used to predict external temperatures. This value is only relevant after user calibration and only for
internal and external conditions identical to those at calibration.
6
The average current from all GPIO balls must not exceed 3 mA per ball.
7
Power figures exclude any load currents to external circuits.
ADuCM322 Data Sheet
Rev. 0 | Page 8 of 23
TIMING SPECIFICATIONS
I
2
C Timing
Table 2. I
2
C Timing in Standard Mode (100 kHz)
Slave
Parameter Description Min Typ Max Unit
t
L
SCL low pulse width 4.7 μs
t
H
SCL high pulse width 4.0 ns
t
SHD
Start condition hold time 4.0 μs
t
DSU
Data setup time 250 ns
t
DHD
Data hold time (SDA held internally for 300 ns after falling edge of SCL) 0 3.45 μs
t
RSU
Setup time for repeated start 4.7 μs
t
PSU
Stop condition setup time 4.0 μs
t
BUF
Bus-free time between a stop condition and a start condition 4.7 μs
t
R
Rise time for both SLC and SDA 1 μs
t
F
Fall time for both SLC and SDA 15 300 ns
t
VD;DAT
Data valid time 3.45 μs
t
VD;ACK
Data valid acknowledge time 3.45 μs
Table 3. I
2
C Timing in Fast Mode (400 kHz)
Slave
Parameter Description Min Typ Max Unit
t
L
SCL low pulse width 1.3 μs
t
H
SCL high pulse width 0.6 ns
t
SHD
Start condition hold time 0.3 μs
t
DSU
Data setup time 100 ns
t
DHD
Data hold time (SDA held internally for 300 ns after falling edge of SCL) 0 μs
t
RSU
Setup time for repeated start 0.6 μs
t
PSU
Stop condition setup time 0.3 μs
t
BUF
Bus-free time between a stop condition and a start condition 1.3 μs
t
R
Rise time for both SCL and SDA 20 300 ns
t
F
Fall time for both SCL and SDA 15 300 ns
t
VD;DAT
Data valid time 0.9 μs
t
VD;ACK
Data valid acknowledge time 0.9 μs
Figure 2. I
2
C Compatible Interface Timing
SDA (I/O)
MSB LSB ACK MSB
1982–71
SCL (I)
PS
START
CONDITION
REPEATED
START
STOP
CONDITION
S(R)
t
DSU
t
H
t
L
t
SHD
t
PSU
t
DSU
t
BUF
t
DHD
t
VD; DAT
t
VD; ACK
t
R
t
F
t
F
t
R
t
DHD
t
RSU
13754-010
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ADUCM322BBCZ-RL

Mfr. #:
Buy ADUCM322BBCZ-RL
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3
Lifecycle:
New from this manufacturer.
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