Data Sheet ADuCM322
Rev. 0 | Page 21 of 23
APPLICATIONS INFORMATION
RECOMMENDED CIRCUIT AND COMPONENT
VALUES
Figure 13 shows a typical connection diagram for the
ADuCM322.
Supplies and regulators must be adequately decoupled
with capacitors connected between the AVDDx, DVDD_x,
AVDD_REGx, IOVDDx, and VDD1 balls and their associated
GND balls (AGNDx, IOGNDx, and DGNDx). Table 10
indicates which ground balls are paired with which supply balls.
There are four digital supply balls: IOVDD1, IOVDD2, IOVDD3,
and VDD1. Decouple these balls with a 100 nF capacitor placed
as near as possible to each of the four balls and their associated
ground balls (IOGNDx and AGND1, respectively). In addition,
place a 10 μF capacitor conveniently near to these balls.
Similarly, the analog supply balls, AVDD3 and AVDD4, each
require a 100 nF capacitor placed as near as possible to each ball
and its associated AGNDx ball, and place a 10 μF capacitor
conveniently near to these balls.
The ADC reference requires a 4.7 μF capacitor placed between
ADC_REFP and ADC_REFN and located as near as possible to
each ball. ADC_REFN must be connected directly to AGND4.
The ADuCM322 contains four internal regulators. These
regulators require external decoupling capacitors. The
DVDD_1V8 and DVDD_2V5 balls each require a 470 nF
capacitor to DGND1 and IOGND3, respectively. AVDD_REG0
and AVDD_REG1 each require a decoupling capacitor to
AGND4. The AVDD_REG1 output ball must be connected to
Ball A3, Ball A4, Ball A8, and Ball A9.
Connect the IREF ball to DGND via a standard 3.3 kΩ resistor.
Take care in the layout to ensure that currents flowing from the
ground end of each decoupling capacitor to its associated
ground ball share as little track as possible with other ground
currents on the printed circuit board.
ADuCM322 Data Sheet
Rev. 0 | Page 22 of 23
Figure 13. Recommended Circuit and Component Values
RESET
RESET
ADC_REFP
GND
DGND
SWDIO
TX
SWCLK
AVDD
AVDD3
AVD
D4
VREF_1V2
IREF
ADC_REFN
AVDD_REG0
AVDD_REG1
AGND1
AGND3
AGND2
F9
L11
K11
A11
F11
H11
L7
K7
J5
F10
AGND4
3.3k
0.47µF
4.7µF
0.47µF 0.47µF
B2
C1
E11
P1.1/SOUT/PLACLK1/PLAI[5]
J2
SWDIO
H2
A3
A9
12pF
DGND
DGND
ADuCM322
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
XTALO
XTALI
RESET
RESET
A4
A8
B4
B8
B5
VDD1
RESERVED
B7
SWCLK
P1.0/SIN/ECLKIN/PLAI[4]
P2.3/BM
K1
IOVDD1
IOVDD3
IOVDD2
VDD1
DVDD_1V8
DVDD_2V5
DGND1
DGND2
IOGND1
IOGND2
IOGND3
10k
D
V
DD
V
DD1
0.47µF
0.47µF
VDD1
10k
10k
VIN
VOUT
E
N/UVLO
GND
AVDD
DVDD
AGND
DGND
AGND
ADP7102ARDZ3.3
VIN
SENSE/AD
J
PG
VDD1
DGND DGND1
10µF
12pF
DGND
NC
DVDD
AGND
AGND1
K2
E10
B10
E9
B9
C3
INTERFACE BOARD CONNECTOR
RX
NC
NC
NC
NC
AVDD_REG1
D10
G11
L6
B6
A6
B1
D11
J1
K6
L2
L1
13754-009
0.1µF
0.1µF0.1µF
10µF
0.1µF
10µF
0.1µF10µF
1.6
1.6
Data Sheet ADuCM322
Rev. 0 | Page 23 of 23
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
Figure 14. 96-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-96-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option Downloader Ordering Quantity
ADuCM322BBCZ −40°C to +105°C 96-Ball CSP_BGA BC-96-2 MDIO 429
ADuCM322BBCZ-RL −40°C to +105°C 96-Ball CSP_BGA BC-96-2 MDIO 2,500
EV-ADuCM322QSPZ
Evaluation Board with QuickStart
Development System
MDIO 1
1
Z = RoHS Compliant Part.
I
2
C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
6.10
6.00 SQ
5.90
5.00 REF
SQ
0.35
0.30
0.25
04-02-2013-A
COPLANARITY
0.08
A
B
C
D
E
F
G
H
J
K
L
7
63
21
5
4
BALL DIAMETER
0.50
BSC
0.50
REF
DETAIL A
A1 BALL
CORNER
A1 BALL
CORNER
DETAIL A
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
1.200
1.083
1.000
89
1011
COMPLIANT TO JEDEC STANDARDS MO-195-AC
WITH THE EXCEPTION TO BALL COUNT.
0.223 NOM
0.173 MIN
0.93
0.86
0.79
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13754-0-2/16(0)
www.analog.com/ADuCM322

ADUCM322BBCZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3
Lifecycle:
New from this manufacturer.
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