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EPF6010ATI100-2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
®
Altera Corporation 1
FLEX 6000
Programmable Logic
Device Family
March 2001, ver. 4.1 Data Sheet
A-DS-F6000-04.1
Features...
■ Provides an ideal low-cost, programmable alternative to high-
volume gate array applications and allows fast design changes
during prototyping or design testing
■ Product features
– Register-rich, look-up table- (LUT-) based architecture
– OptiFLEX
®
architecture that increases device area efficiency
– Typical gates ranging from 5,000 to 24,000 gates (see Table 1)
– Built-in low-skew clock distribution tree
– 100% functional testing of all devices; test vectors or scan chains
are not required
■ System-level features
– In-circuit reconfigurability (ICR) via external configuration
device or intelligent controller
– 5.0-V devices are fully compliant with peripheral component
interconnect Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
–MultiVolt
TM
I/O interface operation, allowing a device to bridge
between systems operating at different voltages
– Low power consumption (typical specification less than 0.5 mA
in standby mode)
– 3.3-V devices support hot-socketing
Note:
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.
Table 1. FLEX 6000 Device Features
Feature EPF6010A EPF6016 EPF6016A EPF6024A
Typical gates (1) 10,000 16,000 16,000 24,000
Logic elements (LEs) 880 1,320 1,320 1,960
Maximum I/O pins 102 204 171 218
Supply voltage (V
CCINT
) 3.3 V 5.0 V 3.3 V 3.3 V
2 Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
...and More
Features
■ Powerful I/O pins
– Individual tri-state output enable control for each pin
– Programmable output slew-rate control to reduce switching
noise
– Fast path from register to I/O pin for fast clock-to-output time
■ Flexible interconnect
–FastTrack
®
Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed, high-fan-
in logic functions (automatically used by software tools and
megafunctions)
– Tri-state emulation that implements internal tri-state networks
– Four low-skew global paths for clock, clear, preset, or logic
signals
■ Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs, Sun
SPARCstations, and HP 9000 Series 700/800
■ Flexible package options
– Available in a variety of packages with 100 to 256 pins, including
the innovative FineLine BGA
TM
packages (see Table 2)
–SameFrame
TM
pin-compatibility (with other FLEX
®
6000 devices)
across device densities and pin counts
– Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and
ball-grid array (BGA) packages (see Table 2)
– Footprint- and pin-compatibility with other FLEX 6000 devices
in the same package
■ Additional design entry and simulation support provided by
EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules
(LPM), Verilog HDL, VHDL, DesignWare components, and other
interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, VeriBest, and Viewlogic
Table 2. FLEX 6000 Package Options & I/O Pin Count
Device 100-Pin
TQFP
100-Pin
FineLine BGA
144-Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
256-Pin
BGA
256-pin
FineLine BGA
EPF6010A 71 102
EPF6016 117 171 199 204
EPF6016A 81 81 117 171 171
EPF6024A 117 171 199 218 219
Altera Corporation 3
FLEX 6000 Programmable Logic Device Family Data Sheet
General
Description
The Altera
®
FLEX 6000 programmable logic device (PLD) family provides
a low-cost alternative to high-volume gate array designs. FLEX 6000
devices are based on the OptiFLEX architecture, which minimizes die size
while maintaining high performance and routability. The devices have
reconfigurable SRAM elements, which give designers the flexibility to
quickly change their designs during prototyping and design testing.
Designers can also change functionality during operation via in-circuit
reconfiguration.
FLEX 6000 devices are reprogrammable, and they are 100% tested prior to
shipment. As a result, designers are not required to generate test vectors
for fault coverage purposes, allowing them to focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different gate array designs. FLEX 6000 devices are
configured on the board for the specific functionality required.
Table 3 shows FLEX 6000 performance for some common designs. All
performance values shown were obtained using Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Note:
(1) This performance value is measured as a pin-to-pin delay.
Table 3. FLEX 6000 Device Performance for Common Designs
Application LEs Used Performance Units
-1 Speed
Grade
-2 Speed
Grade
-3 Speed
Grade
16-bit loadable counter 16 172 153 133 MHz
16-bit accumulator 16 172 153 133 MHz
24-bit accumulator 24 136 123 108 MHz
16-to-1 multiplexer (pin-to-pin) (1) 10 12.1 13.4 16.6 ns
16 × 16 multiplier with a 4-stage pipeline 592 84 67 58 MHz
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

EPF6010ATI100-2

Mfr. #:
Buy EPF6010ATI100-2
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Flex 6000 88 LABs 71 IOs
Lifecycle:
New from this manufacturer.
Delivery:
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