OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

EPF6010ATI100-2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
16 Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Either the counter enable or the up/down control may be used for a given
counter. Moreover, the synchronous load can be used as a count enable by
routing the register output into the data input automatically when
requested by the designer.
The second LE of each LAB has a special function for counter mode; the
carry-in of the LE can be driven by a fast feedback path from the register.
This function gives a faster counter speed for counter carry chains starting
in the second LE of an LAB.
The Altera software implements functions to use the counter mode
automatically where appropriate. The designer does not have to decide
how the carry chain will be used.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the LAB-wide signals LABCTRL1 and LABCTRL2. The LE
register has an asynchronous clear that can implement an asynchronous
preset. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear
or preset. Because the clear and preset functions are active-low, the Altera
software automatically assigns a logic high to an unused clear or preset
signal. The clear and preset logic is implemented in either the
asynchronous clear or asynchronous preset mode, which is chosen during
design entry (see Figure 8).
Altera Corporation 17
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 8. LE Clear & Preset Modes
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2.
Asynchronous Preset
An asynchronous preset is implemented with an asynchronous clear. The
Altera software provides preset control by using the clear and inverting
the input and output of the register. Inversion control is available for the
inputs to both LEs and IOEs. Therefore, this technique can be used when
a register drives logic or drives a pin.
In addition to the two clear and preset modes, FLEX 6000 devices provide
a chip-wide reset pin (DEV_CLRn) that can reset all registers in the device.
The option to use this pin is set in the Altera software before compilation.
The chip-wide reset overrides all other control signals. Any register with
an asynchronous preset will be preset when the chip-wide reset is asserted
because of the inversion technique used to implement the asynchronous
preset.
The Altera software can use a programmable NOT-gate push-back
technique to emulate simultaneous preset and clear or asynchronous load.
However, this technique uses an additional three LEs per register.
FastTrack Interconnect
In the FLEX 6000 OptiFLEX architecture, connections between LEs and
device I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
device. This global routing structure provides predictable performance,
even for complex designs. In contrast, the segmented routing in FPGAs
requires switch matrices to connect a variable number of routing paths,
increasing the delays between logic resources and reducing performance.
PRN
DQ
labctrl1 or
labctrl2
Asynchronous Clear
Asynchronous Preset
CLRN
DQ
Chip-Wide Reset
labctrl1 or
labctrl2
Chip-Wide Reset
18 Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
The FastTrack Interconnect consists of column and row interconnect
channels that span the entire device. Each row of LABs is served by a
dedicated row interconnect, which routes signals between LABs in the
same row, and also routes signals from I/O pins to LABs. Additionally,
the local interconnect routes signals between LEs in the same LAB and in
adjacent LABs. The column interconnect routes signals between rows and
routes signals from I/O pins to rows.
LEs 1 through 5 of an LAB drive the local interconnect to the right, while
LEs 6 through 10 drive the local interconnect to the left. The DATA1 and
DATA3 inputs of each LE are driven by the local interconnect to the left;
DATA2 and DATA4 are driven by the local interconnect to the right. The
local interconnect also routes signals from LEs to I/O pins. Figure 9 shows
an overview of the FLEX 6000 interconnect architecture. LEs in the first
and last columns have drivers on both sides so that all LEs in the LAB can
drive I/O pins via the local interconnect.
Figure 9. FastTrack Interconnect Architecture
Note:
(1) For EPF6010A, EPF6016, and EPF6016A devices, n = 144 channels and m = 20 channels; for EPF6024A devices,
n = 186 channels and m = 30 channels.
2
2
10
10
20
5
55
5
5
10
10
Column Interconnect (m Channels) (1)
Local Interconnect (32 Channels)
To/From
Adjacent
LAB
LE 1
through
LE 5
LE 6
through
LE 10
LE 1
through
LE 5
LE 6
through
LE 10
2
2
22 22
10
105 5
5
5
20
5
5
5
55
5
5
To/From
Adjacent
LAB
5
10
10
10
10 10
10
10
10
10
10
5
10
10
Row Interconnect (n Channels) (1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

EPF6010ATI100-2

Mfr. #:
Buy EPF6010ATI100-2
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Flex 6000 88 LABs 71 IOs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet