Altera Corporation 25
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 14. IOE Connection to Column Interconnect
SameFrame
Pin-Outs
3.3-V FLEX 6000 devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support an EPF6016A device in a 100-pin FineLine BGA package or an
EPF6024A device in a 256-pin FineLine BGA package.
The Altera software packages provide support to design PCBs with
SameFrame pin-out devices. Devices can be defined for present and future
use. The Altera software packages generate pin-outs describing how to lay
out a board to take advantage of this migration (see Figure 15).
Row Interconnect
Column Interconnect
Each IOE can drive two
column interconnect channels.
Each IOE data and OE signal is
driven to a local interconnect.
Any LE can drive a
pin through the row
and local interconnect.
IOE
IOE
LAB
FastFLEX I/O: An
LE can drive a
pin through a local
interconnect for faster
clock-to-output times.
26 Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 15. SameFrame Pin-Out Example
Table 6 lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out
feature.
Output
Configuration
This section discusses slew-rate control, the MultiVolt I/O interface,
power sequencing, and hot-socketing for FLEX 6000 devices.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew-rate that can
be configured for low-noise or high-speed performance. A slower
slew-rate reduces system noise and adds a maximum delay of 6.8 ns. The
fast slew-rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew-rate on
a pin-by-pin basis during design entry or assign a default slew rate to all
pins on a device-wide basis. The slew-rate setting affects only the falling
edge of the output.
Designed for 256-Pin FineLine BGA Package
Printed Circuit Board
100-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
100-Pin
FineLine
BGA
256-Pin
FineLine
BGA
Table 6. 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs
Device 100-Pin FineLine BGA 256-Pin FineLine BGA
EPF6016A
vv
EPF6024A
v
Altera Corporation 27
FLEX 6000 Programmable Logic Device Family Data Sheet
MultiVolt I/O Interface
The FLEX 6000 device architecture supports the MultiVolt I/O interface
feature, which allows FLEX 6000 devices to interface with systems of
differing supply voltages. The EPF6016 device can be set for 3.3-V or 5.0-V
I/O pin operation. This device has one set of V
CC
pins for internal
operation and input buffers (VCCINT), and another set for output drivers
(VCCIO).
The VCCINT pins on 5.0-V FLEX 6000 devices must always be connected
to a 5.0-V power supply. With a 5.0-V V
CCINT
level, input voltages are at
TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs.
The VCCIO pins on 5.0-V FLEX 6000 devices can be connected to either a
3.3-V or 5.0-V power supply, depending on the output requirements.
When the VCCIO pins are connected to a 5.0-V power supply, the output
levels are compatible with 5.0-V systems. When the VCCIO pins are
connected to a 3.3-V power supply, the output high is 3.3 V and is
therefore compatible with 3.3-V or 5.0-V systems. Devices operating with
V
CCIO
levels lower than 4.75 V incur a nominally greater timing delay of
t
OD2
instead of t
OD1
.
On 3.3-V FLEX 6000 devices, the VCCINT pins must be connected to a
3.3-V power supply. Additionally, 3.3-V FLEX 6000A devices can interface
with 2.5-V, 3.3-V, or 5.0-V systems when the VCCIO pins are tied to 2.5 V.
The output can drive 2.5-V systems, and the inputs can be driven by 2.5-
V, 3.3-V, or 5.0-V systems. When the VCCIO pins are tied to 3.3 V, the
output can drive 3.3-V or 5.0-V systems. MultiVolt I/Os are not supported
on 100-pin TQFP or 100-pin FineLine BGA packages.
Table 7 describes FLEX 6000 MultiVolt I/O support.
Note:
(1) When V
CCIO
= 3.3 V, a FLEX 6000 device can drive a 2.5-V device that has 3.3-V
tolerant inputs.
Table 7. FLEX 6000 MultiVolt I/O Support
V
CCINT
(V)
V
CCIO
(V)
Input Signal (V) Output Signal (V)
2.53.35.02.53.35.0
3.3 2.5
vvvv
3.3 3.3
vvv
v
(1)
vv
5.0 3.3
vv vv
5.0 5.0
vv v

EPF6010ATI100-2

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Flex 6000 88 LABs 71 IOs
Lifecycle:
New from this manufacturer.
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