Pin description STA8089G
10/31 DocID030710 Rev 1
2.6 Communication interface pins
TP_IF_N 1.2 V O Diff.Test Point for IF – Neg. 6
TP_IF_P 1.2 V O Diff.Test Point for IF – Pos. 5
Table 3. Test/emulated dedicated pins (continued)
Symbol I/O voltage I/O Description STA8089G
Table 4. Communication interface pins
Symbol I/O voltage I/O
Alternative
function
Function Description
STA8089G
SQI_CLK VDDIO_R1
O AF2 (default) SQI_CLK SQI Flash clock
41
— AF0, AF1, AF3 Reserved Reserved
SQI_CEN VDDIO_R1
O AF2 (default) SQI_CEN SQI Flash chip enable
40
— AF0, AF1, AF3 Reserved Reserved
SQI_SIO0/SI VDDIO_R1
I/O AF2 (default) SQI_SIO0/SI SQI Flash data IO 0 / ser. I/ BOOT2
42
— AF0, AF1, AF3 Reserved Reserved
SQI_SIO1/SO VDDIO_R1
I/O AF2 (default) SQI_SIO1/SO SQI Flash data IO 1 / ser. O
43
— AF0, AF1, AF3 Reserved Reserved
SQI_SIO2 VDDIO_R1
I/O AF2 (default) SQI_SIO2 SQI Flash data IO 2
38
— AF0, AF1, AF3 Reserved Reserved
SQI_SIO3 VDDIO_R1
I/O AF2 (default) SQI_SIO3 SQI Flash data IO 3 / BOOT1
39
— AF0, AF1, AF3 Reserved Reserved
CAN1_TX
(1)
VDDIO_R2
O AF0 I2C_CLK I2C clock
1
I/O AF1 GPIO8 General purpose I/O #8
O AF2 (default) CAN1_TX CAN1 transmit data output
— AF3 Reserved Reserved
CAN1_RX
(1)
VDDIO_R2
I/O AF0 I2C_SD I2C serial data
55
I/O AF1 GPIO9 General purpose I/O #9
I/O AF2 (default) CAN1_RX CAN1 receive data input
— AF3 Reserved Reserved
CAN0_TX
(1)
VDDIO_R2
O AF0 (default) CAN0_TX CAN0 transmit data output
51
O AF1 UART0_TX UART0 Tx data
I/O AF2 GPIO7 General purpose I/O #7
O AF3 I2C_CLK I2C clock
