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STA8089G Electrical characteristics
30
Figure 3. 32.768 kHz crystal connection
To drive the 32.768 kHz crystal pins from an external clock source:
Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This
disables the internal inverter, thus reducing the power consumption to minimum.
Drive the RTC_XTI pin with a square signal or a sine wave.
4.8.3 OSCI oscillator specifications
Default supported values are 16.368 MHz, 24 MHz, 26 MHz and 48 MHz.
To enable USB peripheral the 48 MHz is mandatory
4.8.4 ADC specifications
This section gives the AC specification of the 10 bit Successive Approximation Register
ADC embedded in STA8089G device. It is controlled by the ARM9 MCU through a wrapper
and an APB bridge as depicted in Figure 4 and it has a maximum conversion rate of 1MSPS
with 8 muxed analog input channels capability. An internal voltage reference is used and
analog/digital power supplies connections are implemented inside the device without any
needs of dedicated external pins.
Table 22. Characteristics of external slow clock input
Symbol Parameter Min. Typ. Max. Unit
T
JIT
(cc) Cycle-to-cycle jitter -70 70 ps
T
JIT
(per) Period jitter -70 70 ps
Variation -500 500 ppm
T
DUTY
Duty cycle 45 55 %
CL=18pF
CL=18pF
32.768 kHz
Crystal
RTC_XTII
RCT_XTO
Device
Electrical characteristics STA8089G
26/31 DocID030710 Rev 1
Figure 4. SARADC connections
REFP
REFN
AVDD
AGND
VDD
GND
AIN0
AIN1
AIN7
EN
EOC
START
CLK
V
REF
D[9:0]
SARADC
ADC WRAPPER
SEL[2:0]
VINL1 VDD12_MVR
APB
Bridge2
ADC_IN1
ADC_IN2
ADC_IN8
GND
Table 23. SARADC specifications
Symbol Parameter Min. Typ. Max. Unit
V
ADCIN
ADC_IN input range V
GND
-0.3 V
DD_ADC
+0.3 V
V
ADCCR
Conversion range V
GND
—V
REF
V
V
REF
Voltage reference 1.35 1.4 1.45 V
C
IN
Input capacitance
(1)
1. Not tested in production.
5.5 7.0 8.5 pF
R
IN
Input mux resistance (total equivalent
sampling resistance)
(2)
2. Pad input capacitance included.
1.5 2.0 2.5 k
F
CLK
Clock frequency 2.5 15 MHz
CLK
Clock duty cycle 45 50 55 %
T
SUP
Start up time
(1)(3)
3. From EN = 1.
—— 20 μs
T
C
Conversion time 14 cycles
T
S
Sampling time 3 cycles
INL
Performance
< ±2 LSB
DNL < ±2 LSB
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STA8089G Package and packing information
30
5 Package and packing information
5.1 ECOPACK
®
packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
5.2 VFQFPN56 7 x 7 mm package information
Table 24. VFQFPN56 7 x 7 mm package dimensions
Symbol Min. Typ. Max
Common dimensions
A 0.80 0.85 0.90
A1 0 0.01 0.05
A2 0.60 0.65 0.70
A3 0.20 REF
b 0.15 0.20 0.25
D 7.00 BSC
D1 6.75 BSC
D2 5.0 5.1 5.2
E 7.00 BSC
E1 6.75 BSC
E2 5.0 5.1 5.2
e 0.40 BSC
12°
L 0.30 0.40 0.50
N56
Nd 14
Ne 14
P 0.24 0.42 0.60

STA8089GTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
RF Receiver GPS/Galileo/Glonass/Beidou/QZSS receiver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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