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STA8089G General description
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3 General description
3.1 RF front end
The RF front-end is able to down-convert both the GPS-Galileo signal from 1575.42 MHz to
4.092 MHz (4 Fo, being F0 = 1.023 MHz), the GLONASS signal from 1601.718 MHz to
8.57 MHz and the BeiDou signal from 1561.098 MHz to 10.23 MHz.
It embeds high performance LNA minimizing external component count and a LDO to
supply the internal core facilitating requirements for external power supply. A three bits ADC
converts the IF signals to sign (SIGN) and magnitude (MAG0 and MAG1). They can be
sampled or not by SPI. The magnitude bits are internally integrated in order to control the
variable gain amplifiers. The VGA gain can be also set by the SPI interface.
The RF tuner accepts a wide range of reference clocks (10 to 52 MHz) and can generate
64 Fo sampling clock for the baseband and 192 Fo clock for MCU subsystem.
3.2 GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+)
processor
STA8089G integrates G3BB+ proprietary IP, which is the ST last generation high-sensitivity
Baseband processor fully compliant with GPS, Galileo, GLONASS and BeiDou systems.
The baseband receives, from the embedded RF Front-End, two separate IF signals coded
in sign-magnitude digital format on 3 bits and the related clocks. The Galileo/GPS
(GALGPS) and GLONASS/BeiDou (GNSCOM) signals at the base band inputs are
centered on 4.092 MHz, 8.57 MHz and 10.23 MHz.
The baseband processes the two IF signals performing data codification, sample rate
conversion and final frequency conversion to zero IF before acquisition and tracking
correlations.
The baseband processor has the capability of acquire and track the Galileo, GPS,
GLONASS and BeiDou signals in a simultaneous or single way, or a combination of three,
being GLONASS and BeiDou mutually exclusive. The number of tracking channels to be
used is programmable; the not used tracking channels can be powered down.
A complete multi-OS software library is provided by ST to handle GPS processing,
managing satellite acquisition, tracking, pseudo-range calculation and positioning,
generating the output in the standard NMEA message format or in a ST binary format. The
library includes support of ST self-trained assisted GPS (ST-AGPS), a complete and
scalable solution for assisting GPS start-up with autonomous and server-based ephemeris
prediction and extension.
3.3 MCU Subsystem
The implemented sub-system includes an AHB Lite bus matrix.
An ARM946 core is embedded in the sub-system and masters the AHB bus. The totally
available TCM SRAM is 256 KB. The amount of memory on ITCM and DTCM can be
configured by the ARM946 (see Table 6: TCM Configuration). ITCM can be configured as Ni
x 16 KB; DTCM can be configured as 128 + Nd x 16 KB, where Ni + Nd = 8, Ni 1.
General description STA8089G
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3.3.1 AHB slaves
G3 APB port that allows to interface with the G3BB acquisition memory and control
registers.
512 Kbytes ROM
Vectored Interrupt Controller (VIC).
SQI flash memory controller
3 x ARM946 APB peripheral bus (APB1, APB2, APB3).
Vectored Interrupt Controller (VIC)
This Vectored Interrupt Controller (VIC) allows the operative system interrupt handler to
quickly dispatch interrupt service routines in response to peripheral interrupts. It provides a
software interface to the interrupt system. There are up to 64 interrupt lines. The VIC uses a
bit position for each different interrupt source.
The software can control each request line to generate software interrupts. Each interrupt
line can be independently enabled and configured to trigger a non-vectored Normal Interrupt
Request (IRQ) or Fast Interrupt Request (FIQ) to the ARM946 CPU. Sixteen interrupt lines
can also be selected to trigger a vectored IRQ.
The VIC has two operation modes: the user mode and the privilege mode, in order to have
the possibility to set (or not) one level of protection during execution.
FS USB device controller
Full speed USB device with transceiver. It is an AHB slave. When active requires a 48 MHz
clock XTAL_IN.
SQI Flash interface
STA8089G includes a high-performance interface to Serial Quad Interface (SQI) NOR Flash
chips, to support a low-cost simple implementation.
Table 6. TCM Configuration
TCMcfg [2] TCMcfg [1] TCMcfg [0] ITCM DTCM
0 0 0 16 KB 240 KB
0 0 1 32 KB 224 KB
0 1 0 48 KB 208 KB
0 1 1 64 KB 192 KB
1 0 0 80 KB 176 KB
1 0 1 96 KB 160 KB
1 1 0 112 KB 144 KB
1 1 1 128 KB 128 KB
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STA8089G General description
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3.4 APB peripherals
3.4.1 CAN (only STA8089GB and STA8089GBD)
The 2 CAN cores perform communication according to the CAN protocol version 2.0 part A
and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the
physical layer, additional transceiver hardware is required.
CAN consists of the CAN core, message RAM, message handler, control registers and
module. For communication on a CAN network, individual message objects are configured.
The message objects and identifier masks for acceptance filtering of received messages are
stored in the message RAM. All functions concerning the handling of messages are
implemented in the message handler. These functions include acceptance filtering, the
transfer of messages between the CAN core and the message RAM, and the handling of
transmission requests as well as the generation of the module interrupt.
The register set of the CAN can be accessed directly by the CPU through the module
interface. These registers are used to control/configure the CAN core and the message
handler and to access the message RAM.
CAN features
Supports CAN protocol version 2.0 part A and B
32 messages objects
Each message object has its own identifier mask
Maskable interrupt
Disabled automatic re-transmission mode for time triggered CAN applications
Programmable loop-back mode for self-test operation
Two 16-bit module interfaces to the AMBA APB bus from ARM
3.4.2 UART
The UARTx (x = 1|2) performs serial-to-parallel conversion on data asynchronously
received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on
data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are
buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64
data byte with 4-bit status (break, frame, parity, and overrun) for receive.

STA8089GTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
RF Receiver GPS/Galileo/Glonass/Beidou/QZSS receiver
Lifecycle:
New from this manufacturer.
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