STA8089GTR Datasheet STA8089G, STA8089GTR | P16-P18

General description STA8089G

16/31 DocID030710 Rev 1

UART features

The UARTx (x = 1|2) are Universal Asynchronous Receiver/Transmitter that support much

of the functionality of the industry-standard 16C650 UART. The main features are:

 Programmable baud rates up to UARTCLK / 16 (1.5 Mbps with UARTCLK at 24 MHz),

or up to UARTCLK / 8 (3.0 Mbps with UARTCLK at 24 MHz), with fractional baud-rate

generator

 5, 6, 7 or 8 bits of data

 Even, odd, stick or no-parity bit generation and detection

 1 or 2 stop bit generation

 Support of software flow control using programmable Xon/Xoff characters

 False start bit detection

 Line break generation and detection

 Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO

 Programmable FIFO disabling for 1-byte depth data path

These UARTs vary from industry-standard 16C650 on some minor points which are:

 Receive FIFO trigger levels

 The internal register map address space, and the bit function of each register differ

 The deltas of the modem status signals are not available

 1.5 stop bits is not supported

 Independent receive clock feature is not supported

3.4.3 I2C

STA8089G includes an I2C interface configurable as master or slave.

3.4.4 MTU

The 2 Multi Timer Units provide access to eight interrupt generating programmable 32-bit

Free-Running decrementing Counters (FRCs). The FRCs have their own clock input,

allowing the counters to run from a much slower clock than the system clock.

The FRC is the part of the timer that performs the counting. There are four instantiations of

the FRC block in each MTU, allowing eight counts to be performed in parallel. The 32-bit

counter in the FRC is split up into two 16-bit counters.

3.4.5 WDT

Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog

clock is used to generate a regular interrupt (WDOGINT), depending on a programmed

value.

The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt

remains unserviced for the entire programmed period. You can enable or disable the

watchdog unit as required.

Note: Watchdog is stalled when the ARM processor is in Debug mode.

DocID030710 Rev 1 17/31

STA8089G General description

3.4.6 GPIO

The GPIO block provides seven (7) programmable inputs or outputs. Each input or output

can be controlled in two modes:

 software mode through an APB bus interface

 alternate mode, where GPIO becomes a peripheral input or output line

Any GPIO input can be independently enabled or disabled (masked) for interrupt

generation. User can select for each GPIO which edge (rising, falling, both) will trigger an

interrupt.

3.4.7 ADC

10 bit SAR ADC operating at 1.8 V analog supply. It can convert up to 2 single ended

channels with analog input multiplexer at 500KSPS

3.4.8 RTC

This is an always-on power domain dedicated to RTC logic (backup system) with 32 Kbyte

SRAM and supplied with a dedicated voltage regulator.

The RTC provides a high resolution clock which can be used for GPS. It keeps the time

when the system is inactive and can be used to wake the system up when a programmed

alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the

32.768 kHz crystal and a secured time update.

RTC features

 47-bit counter clocked by 32.768 kHz clock

 32-bit for the integer part (seconds) and 15-bit for the fractional part

 The integer part and the fractional part are readable independently

 The counter, once enabled, can be stopped

 Integer part load register (32-bit)

 Fractional part load register (15-bit)

 Load bit to transfer the content of the entire load register (integer+fractional part) to the

47-bit counter. Once set by the MCU this bits is cleared by the hardware to signal to the

MCU that the RTC has been updated.

Electrical characteristics STA8089G

18/31 DocID030710 Rev 1

4 Electrical characteristics

4.1 Parameter conditions

Unless otherwise specified, all voltages are referred to GND.

4.2 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

= 25 °C.

4.3 Typical values

Unless otherwise specified, typical data are based on T

= 25°C, V

ddio

= 1.8 V, V

= 1.20 V.

They are given only as design guidelines and are not tested.

4.4 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

4.5 Absolute maximum ratings

This product contains devices to protect the inputs against damage due to high static

voltages, however it is advisable to take normal precautions to avoid application of any

voltage higher than the specified maximum rated voltages.

Table 7 lists the absolute maximum rating.

Table 7. Voltage characteristics

Symbol Parameter Min. Max. Unit

CC_CHAIN

Analog supply voltage for RF chain (1.2 V) -0.3 1.32 V

CC_PLL

Analog supply voltage for PLL RF (1.2 V) -0.3 1.32 V

CC_RF

Analog supply voltage for RF (1.2 V) -0.3 1.32 V

DDD

Power supply pins for the core logic. -0.3 1.32 V

DDIO_R1

Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V) -0.3 3.63 V

DDIO_R2

Digital supply voltage for I/O ring 2 (3.3 V) -0.3 3.63 V

INB

Backup LDO input supply voltage (1.6 V to 4.3 V) -0.3 4.8 V

INL1

LDO1 input supply voltage (1.8 V) -0.3 1.98 V

INL2

LDO2 input supply voltage (1.6 V to 4.3 V) -0.3 4.8 V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

STA8089GTR

Mfr. #:

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RF Receiver GPS/Galileo/Glonass/Beidou/QZSS receiver

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STA8089GTR

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