2©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1V
DDA
Power Analog supply pin.
2, 25 V
DD
Power Core supply pin.
3,
4
XTAL_OUT,
XTAL_IN
Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
5, 13,
20, 24, 27
GND Power Power supply ground.
6 REF_SEL Input Pulldown Reference select pin. See Table 3C. LVCMOS/LVTTL interface levels.
7 REF_IN Input Pulldown Single-ended 25MHz reference clock input. LVCMOS/LVTTL interface levels.
8,
14,
16
F_SELB2,
F_SELB1,
F_SELB0
Input Pulldown
Frequency select pins for Bank B outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
9 nREF_OE Input Pullup
Active low REF_OUT enable/disable pin. See Table 3D.
LVCMOS/LVTTL interface levels.
10 V
DDO_REF
Power Output supply pin for REF_OUT clock output.
11 REF_OUT Output Single-ended LVCMOS/LVTTL reference clock output.
12, 26 nc Unused No connect.
15 MR/nOE Input Pulldown
Active HIGH Master Reset. Active LOW output enable. See Table 3E.
LVCMOS/LVTTL interface levels.
17 V
DDO_B
Power Output supply pin for QBx outputs.
18, 19 QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
21 V
DDO_A
Power Output supply pin for QAx outputs.
22, 23 QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
28,
32
F_SELA0,
F_SELA2
Input Pullup
Frequency select pins for Bank A outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
29 F_SELA1 Input Pulldown
Frequency select pin for Bank A outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
30,
31
SLEW0,
SLEW1
Input Pulldown
Slew rate select pins for LVCMOS/LVTTL clock output. See Table 3B.
LVCMOS/LVTTL interface levels.
