13©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
Schematic Layout
Figure 3 shows an example 840S05I application schematic. This
schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
In this schematic, the device is operated at VDD=VDDA = 3.3V and
VDDO_A, VDDO_B and VDDO_REF=2.5V. An 18pF parallel
resonant 25MHz crystal is used with the recommended load
capacitors C1 = 33pF and C2 = 27pF for frequency accuracy.
Depending on the parasitic capacity on the crystal terminals of the
printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. This will require
adjusting C1 and C2. For this device, the crystal load capacitors are
required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 840S05I provides separate
power supply pins to isolate any high switching noise from coupling
into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µf capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of
the PCB.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
