840S05AYILF Datasheet 840S05AYILF, 840S05AYILFT | P10-P12

840S05I Data Sheet

Parameter Measurement Information, continued

Output Duty Cycle/Pulse Width/Period

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k resistor can be used.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k resistor can be tied

from XTAL_IN to ground.

REF_IN Input

For applications not requiring the use of the reference clock, it can

be left floating. Though not required, but for additional protection, a

1k resistor can be tied from the REF_IN to ground.

Outputs:

LVCMOS Outputs

All unused LVCMOS outputs can be left floating. There should be no

trace attached.

PERIOD

odc =

DDO_X

x 100%

QA[1:0],

QB[1:0]

840S05I Data Sheet

Overdriving the XTAL Interface

The XTAL_IN input can be overdriven by an LVCMOS driver or by

one side of a differential driver through an AC coupling capacitor. The

XTAL_OUT pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 1A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50

 applications,

R1 and R2 can be 100

. This can also be accomplished by removing

R1 and changing R2 to 50. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 1B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the XTAL_IN input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a quartz crystal as the input.

Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface

VCC

XTAL_OUT

XTAL_IN

100

Zo = 50 ohmsRs

Zo = Ro + Rs

.1uf

LVCMOS Driver

XTA L_ OU T

XTA L_ I N

Zo = 50 ohms

.1uf

LVPECL Driver

Zo = 50 ohms

840S05I Data Sheet

EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 2. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, refer to the Application Note

on the Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadframe Base Package, Amkor Technology.

Figure 2. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

GROUND PLANE

LAND PATTERN

SOLDER

THERMAL VIA

EXPOSED HEAT SLUG

(GROUND PAD)

PIN PAD

SOLDER

PIN PAD

SOLDER

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

840S05AYILF

Mfr. #:

Buy 840S05AYILF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner Crystal LVCMOS LVTTL Freq Synth

Lifecycle:

New from this manufacturer.

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840S05AYILF

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