16©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 36.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.817W * 36.2°C/W = 114.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance
JA
for 32 Lead TQFP, E-Pad, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 36.2°C/W 30.6°C/W 29.2°C/W
17©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
Reliability Information
Table 8.
JA
vs. Air Flow Table for a 32 Lead TQFP, E-Pad
Transistor Count
The transistor count for 840S05I is: 2395
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 36.2°C/W 30.6°C/W 29.2°C/W
18©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead TQFP, E-Pad
Table 9. Package Dimensions 32 Lead TQFP, E-Pad
Reference Document: JEDEC Publication 95, MS-026
-HD VERSION
EXPOSED PAD DOWN
-TAB, EXPOSED PART OF CONNECTION BAR OR TIE BAR
0.20
TAB
JEDEC Variation: ABA - HD
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 32
A 1.20
A1 0.05 0.10 0.15
A2 0.95 1.00 1.05
b 0.30 0.35 0.40
c 0.09 0.20
D, E 9.00 Basic
D1, E1 7.00 Basic
D2, E2 5.60 Ref.
D3, E3 3.0 3.5 4.0
e 0.80 Basic
L 0.45 0.75
ccc 0.10

840S05AYILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Crystal LVCMOS LVTTL Freq Synth
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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