7©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
AC Electrical Characteristics
Table 6A. AC Characteristics, V
DD
= V
DDO_REF
= V
DDO_A
= V
DDO_B
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO_A, _B, _REF
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: Characterized using a 25MHz Crystal input. REF_OUT is disabled.
NOTE 5: A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output
Frequency
QA[1:0] 33.33 166.67 MHz
QB[1:0] 33.33 166.67 MHz
tsk(o)
Output Skew;
NOTE 1, 2
QA[1:0] or
QB[1:0]
f
OUT
125MHz, 25MHz Crystal Input 180 ps
tsk(b)
Bank Skew;
NOTE 2, 3
QA[1:0] or
QB[1:0]
SLEW[1:0] = 00 35 ps
tjit(per) Period Jitter, RMS; NOTE 4
f
OUT
= 125MHz, SLEW[1:0] = 00 3.4 ps
f
OUT
= 125MHz, SLEW[1:0] = 01 3.4 ps
f
OUT
= 125MHz, SLEW[1:0] = 10 3.5 ps
f
OUT
= 125MHz, SLEW[1:0] = 11 4.6 ps
t
SLEW
Slew Rate;
NOTE 5
QA[1:0] or
QB[1:0]
SLEW[1:0] = 00,
Rise/Fall Time: 20% to 80%
3.5 5.0 V/ns
QA[1:0] or
QB[1:0]
SLEW[1:0] = 01,
Rise/Fall Time: 20% to 80%
2.6 3.8 V/ns
QA[1:0] or
QB[1:0]
SLEW[1:0] = 10,
Rise/Fall Time: 20% to 80%
1.8 2.7 V/ns
QA[1:0] or
QB[1:0]
SLEW[1:0] = 11,
Rise/Fall Time: 20% to 80%
1.0 1.7 V/ns
t
L
PLL Lock Time SLEW[1:0] = 00 20 ms
odc
Output Duty
Cycle
QA[1:0] or
QB[1:0]
25MHz Crystal Input,
SLEW[1:0] = 00
45 55 %
8©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
Table 6B. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO_REF
= V
DDO_A
= V
DDO_B
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO_A, _B, _REF
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: Characterized using a 25MHz Crystal input. REF_OUT is disabled.
NOTE 5: A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output
Frequency
QA[1:0] 33.33 166.67 MHz
QB[1:0] 33.33 166.67 MHz
tsk(o)
Output Skew;
NOTE 1, 2
QA[1:0] or
QB[1:0]
f
OUT
125MHz, 25MHz Crystal Input 210 ps
tsk(b)
Bank Skew;
NOTE 2, 3
QA[1:0] or
QB[1:0]
SLEW[1:0] = 00 45 ps
tjit(per) Period Jitter, RMS; NOTE 4
f
OUT
= 125MHz, SLEW[1:0] = 00 3.5 ps
f
OUT
= 125MHz, SLEW[1:0] = 01 3.6 ps
f
OUT
= 125MHz, SLEW[1:0] = 10 4.1 ps
f
OUT
= 125MHz, SLEW[1:0] = 11 6.3 ps
t
SLEW
Slew Rate;
NOTE 5
QA[1:0] or
QB[1:0]
SLEW[1:0] = 00,
Rise/Fall Time: 20% to 80%
3.0 4.5 V/ns
QA[1:0] or
QB[1:0]
SLEW[1:0] = 01,
Rise/Fall Time: 20% to 80%
2.2 3.4 V/ns
QA[1:0] or
QB[1:0]
SLEW[1:0] = 10,
Rise/Fall Time: 20% to 80%
1.6 2.6 V/ns
QA[1:0] or
QB[1:0]
SLEW[1:0] = 11,
Rise/Fall Time: 20% to 80%
0.9 1.7 V/ns
t
L
PLL Lock Time SLEW[1:0] = 00 25 ms
odc
Output Duty
Cycle
QA[1:0] or
QB[1:0]
25MHz Crystal Input,
SLEW[1:0] = 00
45 55 %
9©2016 Integrated Device Technology, Inc Revision A April 11, 2016
840S05I Data Sheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load Test Circuit
Output Skew
RMS Period Jitter
3.3V Core/2.5V LVCMOS Output Load Test Circuit
Bank Skew
Output Slew Rate
SCOPE
Qx
GND
1.65V±5%
-1.65V±5%
V
DDA
1.65V±5%
V
DD,
V
DDO_A,
V
DDO_B,
V
DDO_REF
Qx
Qy
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
Histogram
SCOPE
Qx
GND
V
DD
1.25V±5%
-1.25V±5%
2.05V±5%
V
DDA
2.05V±5%
V
DDO_A,
V
DDO_B,
V
DDO_REF
t
sk(b)
V
DDO_X
2
V
DDO_X
2
QX0
QX1
Where X is either Bank A or Bank B
20%
80%
80%
20%
t
R
t
F
V
F
V
R
t
SLEW
= V
R
/t
R
QA[1:0],
QB[1:0]

840S05AYILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Crystal LVCMOS LVTTL Freq Synth
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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