©2014 Integrated Device Technology, Inc.
AUGUST 2014
DSC 2654/13
1
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
2654 drw 01
I/O
0L
-I/O
8L
CE
L
OE
L
R/W
L
INT
L
BUSY
R
I/O
0R
-I/O
8R
A
10R
A
0R
INT
R
CE
R
OE
R
(2)
(1,2)
(1,2)
(2)
R/W
R
CE
R
OE
R
R/W
R
11
11
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
NOTES:
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.
70125 (SLAVE): BUSY is input.
2. INT is non-tri-stated push-pull output.
Functional Block Diagram
Features
High-speed access
Commercial: 25/35/55ns (max.)
Industrial: 35ns (max.)
Low-power operation
IDT70121/70125S
Active: 675mW (typ.)
Standby: 5mW (typ.)
IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
Fully asychronous operation from either port
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
On-chip port arbitration logic (IDT70121 only)
BUSY output flag on Master; BUSY input on Slave
INT flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (±10%) power supply
Available in 52-pin PLCC
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
2
Pin Configurations
(1,2,3)
Description
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static
RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual-
Port RAM or as a “MASTER” Dual-Port RAM together with the IDT70125
“SLAVE” Dual-Port in 18-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power-down
feature, controlled by CE, permits the on-chip circuitry of each port to enter
a very low standby power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for
Data/Control and parity bits at the user’s option. This feature is especially
useful in data communications applications where it is necessary to use a
parity bit for transmission/reception error checking.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 675mW of power. Low-power (L)
versions offer battery backup data retention capability with each port
typically consuming 200µW from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC.
NOTES:
1. All V
CC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Maximum Operating Temperature
and Supply Voltage
(1)
Recommended DC
Operating Conditions
Absolute Maximum Ratings
(1)
Capacitance (TA = +25°C, f = 1.0MHz)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to
< 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. V
IL > -1.5V for pulse width less than 10ns.
2. V
TERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter T
A. This is the "instant on" case temperature.
NOTE:
1. This parameter is determined by device characterization but is not production
tested.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VCC = 5.0V ± 10%)
NOTE:
1. At Vcc
< 2.0V leakages are undefined.
Symbol Rating Commercial
& Industrial
Unit
V
TE RM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0 V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output
Current
50 mA
2654 tbl 01
Grade Ambient
Temperature
GND Vcc
Commercial 0
O
C to +70
O
C0V 5.0V
+
10%
Industrial -40
O
C to +85
O
C0V 5.0V
+
10%
2654 tbl 02
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
____
6.0
(2 )
V
V
IL
Input Low Voltage -0.5
(1 )
____
0.8 V
2654 tbl 03
Symbol Parameter
Conditions
(1 )
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Output Capacitance V
OUT
= 3dV 10 pF
2654 tbl 04
Symbol Parameter Test Conditions
70121S
70125S
70121L
70125L
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
A
|I
LO
| Output Leakage Current V
CC
= 5.5V, CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
A
V
OL
Output Low Voltage I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2654 tbl 05

70121L35J8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 2KX9 DUAL PORT MASTR W/IN
Lifecycle:
New from this manufacturer.
Delivery:
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