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70121L35J8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side
(1,2,4)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3.
tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last,
tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, CE = VIL, and OE = VIL, and the address is valid prior to other coincidental with CE transition LOW.
Timing Waveform of Read Cycle No. 2, Either Side
(5)
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2654 drw 05
t
BDD
(3,4)
BUSY
OUT
CE
t
ACE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2654 drw 06
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
t
AOE
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, t
WC = tBAA + tWP, since R/W = VIL must occur after tBAA .
4. 'X' in part numbers indicates power rating (S or L).
5. The specified t
DH must be met by the device supplying write date to the RAM under all operating conditions.
Although t
DH and t
OW
values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW.
6. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required t
DW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
WP.
Symbol Parameter
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
UnitMin. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time
(4)
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write 20
____
30
____
ns
t
AW
Address Valid to End-of-Write 20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(6 )
20
____
30
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 12
____
20
____
ns
t
HZ
Output High-Z Time
(1 , 2 ,3 )
____
10
____
15 ns
t
DH
Data Hold Time
(5 )
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,3)
____
10
____
15 ns
t
OW
Output Active from End-of-Write
(1,2,3,5)
0
____
0
____
ns
2654 tbl 10a
Symbol Parameter
70121X55
70125X55
Com'l Only
UnitMin. Max.
WRITE CYCLE
t
WC
Write Cycle Time
(4)
55
____
ns
t
EW
Chip Enable to End-of-Write 40
____
ns
t
AW
Address Valid to End-of-Write 40
____
ns
t
AS
Address Set-up Time 0
____
ns
t
WP
Write Pulse Width
(6)
40
____
ns
t
WR
Write Recovery Time 0
____
ns
t
DW
Data Valid to End-of-Write 20
____
ns
t
HZ
Output High-Z Time
(1,2,3)
____
30 ns
t
DH
Data Hold Time
(5)
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,3)
____
30 ns
t
OW
Output Active from End-of-Write
(1,2,3,5)
0
____
ns
2654 tbl 10b
9
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a CE = VIL and a R/W = VIL
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required t
DW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
WP.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1,5)
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
R/W
t
WC
t
HZ
t
AW
t
HZ
t
AS
t
WP
DATA
OUT
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE
t
WZ
(4) (4)
t
WR
2654 drw 07
(3)
(7)
(2)
(6)
(7)
(7)
CE
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
2654 drw 08
(6) (2)
(3)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

70121L35J8

Mfr. #:
Buy 70121L35J8
Manufacturer:
IDT
Description:
SRAM 2KX9 DUAL PORT MASTR W/IN
Lifecycle:
New from this manufacturer.
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