6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY.
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER IDT70121)
t
BAA
BUSY Access Time from Address
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20 ns
t
WDD
Write Pulse to Data Delay
(1)
50 60
t
DDD
Write Data Valid to Read Data Delay
(1)
35 45
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5)
15
____
20
____
ns
BUSY INPUT TIMING (For SLAVE IDT70125)
t
WB
Write to BUSY Input
(4)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45 ns
2654 tbl 11a
70121X55
70125X55
Com'l Only
Symbol Parameter Min. Max. Unit
BUSY TIMING (For MASTER IDT 70121)
t
BAA
BUSY Access Time from Address
____
30 ns
t
BDA
BUSY Disable Time from Address
____
30 ns
t
BAC
BUSY Access Time from Chip Enable
____
30 ns
t
BDC
BUSY Disable Time from Chip Enable
____
30 ns
t
WDD
Write Pulse to Data Delay
(1)
80
t
DDD
Write Data Valid to Read Data Delay
(1)
65
t
APS
Arbitration Priority Set-up Time
(2)
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
45 ns
t
WH
Write Hold After BUSY
(5)
20
____
ns
BUSY INPUT TIMING (For SLAVE IDT 70125)
t
WB
Write to BUSY Input
(4)
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
80 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
65 ns
2654 tbl 11b
11
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
tAPS
ADDR 'A'
DATAIN'A'
MATCH
tWC
tWP
R/W'A'
ADDR'B'
DATAOUT 'B'
MATCH
BUSY
'B'
tBDA
tDW
tDH
VALID
VALID
tDDD
(4)
tWDD
tBDD
2654 drw 09
(1)
Timing Waveform of BUSY Arbitration Controlled by CE Timing
(1)
Timing Waveform of Write with Port-to-Port Read and BUSY
(1,2,3)
Timing Waveform of Write with BUSY
(3)
NOTES:
1. t
WH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port 'B' blocking R/W
'B', until BUSY'B' goes HIGH.
3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS is ignored for Slave (IDT70125).
2. CE
L = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
2654 drw 10
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
,
t
BDC
ADDR
"A
and
B"
BUSY
"B"
CE
"A"
t
APS
(2)
t
BAC
ADDRESSES MATCH
CE
"B"
2654 drw 11
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t
APS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
12
Timing Waveform of BUSY Arbritration Controlled by Address
(1)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
t
BAA
ADDR
'A'
BUSY
'B'
ADDRESSES MATCH ADDRESSES DO NOT MATCH
t
RC
OR
t
WC
t
APS
(2)
t
BDA
ADDR
'B'
2654 drw 12
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit
INTERRUPT TIMING
t
AS Address Set-up Time 0
____
0
____
ns
t
WR Write Recovery Time 0
____
0
____
ns
t
INS Interrupt Set Time
____
25
____
35 ns
t
INR Interrupt Reset Time
____
25
____
35 ns
2654 tbl 12a
70121X55
70125X55
Com'l Only
Symbol Parameter Min. Max. Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
ns
t
WR
Write Recovery Time 0
____
ns
t
INS
Interrupt Set Time
____
45 ns
t
INR
Interrupt Reset Time
____
45 ns
2654 tbl 12b
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If
tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).

70121L35J8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 2KX9 DUAL PORT MASTR W/IN
Lifecycle:
New from this manufacturer.
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