6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
14
Functional Description
The IDT70121/125 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70121/125 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INT
L) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CE = R/W = VIL per Truth Table
II. The left port clears the interrupt by access address location 7FE access
when CE
R = OER = VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
7FF (HEX) and to clear the interrupt flag (INT
R), the right port must access
the memory location 7FF. The message (9 bits) at 7FE or 7FF is user-
defined, since it is an addressable SRAM location. If the interrupt function
is not used, address locations 7FE and 7FF are not used as mail boxes,
but as part of the random access memory. Refer to Table II for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by using the IDT70125
(SLAVE). In the IDT70125, the BUSY pin operates solely as a write inhibit
input pin. Normal operation can be programmed by tying the BUSY pins
HIGH. Once in slave mode the BUSY pin operates solely as a write inhibit
input pin. If desired, unintended write operations can be prevented to a
port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70121/125 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these RAMs are being expanded in depth, then the BUSY indication for
the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70121/125 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the BUSY signal as a write inhibit signal. Thus on the IDT70121 RAM the
BUSY pin is an output of the part, and the BUSY pin is an input of the
IDT70125 as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
Figure 3. Busy and chip enable routing for both width and depth
expansion with 70121 (Master) and 70125 (Slave) RAMs.
2654 drw 14
MASTER
Dual Port
RAM
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
R
CE
BUSY
L
BUSY
R
D
E
C
O
D
E
R
BUSY
L
BUSY
L
BUSY
L
BUSY
L
,
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
