6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,4)
(VCC = 5V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of
input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, T
A=+25°C for Typ, and is not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
f = f
MAX
(2 )
COM'L S
L
135
135
260
220
135
135
250
210
mA
IND S
L
___
___
___
___
135
135
275
250
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
= CE
"B"
= V
IH
f = f
MAX
(2 )
COM'L S
L
30
30
65
45
30
30
65
45
mA
IND S
L
___
___
___
___
30
30
80
65
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5 )
Active Port Outputs Disabled,
f=f
MAX
(2 )
COM'L S
L
80
80
175
145
80
80
165
135
mA
IND S
L
___
___
___
___
80
80
190
165
I
SB3
Full Standby Current (Both Ports
- CMOS Level Inputs)
CE
"A"
and CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
VIN <
0.2V, f = 0
(3 )
COM'L S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
IND S
L
___
___
___
___
1.0
0.2
15
5
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5 )
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2 )
COM'L S
L
70
70
170
140
70
70
160
130
mA
IND
S
L
___
___
___
___
70
70
185
160
2654 tbl 06a
70121X55
70125X55
Com'l Only
Symbol Parameter Test Condition Version Typ. Max. Unit
I
CC
Dynamic Operating Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
f = f
MAX
(2)
COM'L S
L
135
135
240
200
mA
IND S
L
___
___
___
___
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
= CE
"B"
= V
IH
f = f
MAX
(2)
COM'L S
L
30
30
65
45
mA
IND S
L
___
___
___
___
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
COM'L S
L
80
80
155
125
mA
IND S
L
___
___
___
___
I
SB3
Full Standby Current
(Both Ports - CMOS Level
Inputs)
CE
"A"
and CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
COM'L S
L
1.0
0.2
15
5
mA
IND S
L
___
___
___
___
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
COM'L S
L
70
70
150
120
mA
IND S
L
___
___
___
___
2654 tbl 06b
5
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Data Retention Characteristics (L Version Only)
Data Retention Waveform
AC Test Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
NOTES:
1. V
CC = 2V, TA = +25°C, and are not production tested.
2. t
RC = Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
V
DR
2V
DATA RETENTION MODE
Vcc
CE
4.5V
t
CDR
t
R
V
IH
V
DR
V
IH
4.5V
2654 drw 03
1250Ω
30pF
775Ω
DATA
OUT
BUSY
INT
5V
5V
1250Ω
5pF*
775Ω
DATA
OUT
2654 drw 04
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
for Data Retention 2.0
___ ___
V
I
CCDR
Data Retention Current
V
CC
= 2V, CE > V
CC
- 0.2V IND.
___
100 4000
µA
t
CDR
(3 )
Chip Deselect to Data Retention Time V
IN
> V
CC
- 0.2V or V
IN
< 0.2 COM'L.
___
100 1500
t
R
(3)
Operation Recovery Time t
RC
(2)
___ ___
V
2654 tbl 07
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 08
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
6
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 25
____
35
____
ns
t
AA
Address Access Time
____
25
____
35 ns
t
ACE
Chip Enable Access Time
____
25
____
35 ns
t
AOE
Output Enable Access Time
____
12
____
25 ns
t
OH
Output Hold from Address Change 0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
15 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50 ns
2654 tbl 09a
70121X55
70125X55
Com'l Only
UnitSymbol Parameter Min. Max.
READ CYCLE
t
RC
Read Cycle Time 55
____
ns
t
AA
Address Access Time
____
55 ns
t
ACE
Chip Enable Access Time
____
55 ns
t
AOE
Output Enable Access Time
____
35 ns
t
OH
Output Hold from Address Change 0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
30 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50 ns
2654 tbl 09b

70121L35J8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 2KX9 DUAL PORT MASTR W/IN
Lifecycle:
New from this manufacturer.
Delivery:
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