XRT81L27
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SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
18
1.3 O
PERATION
OF
THE
C
OMMAND
C
ONTROL
R
EGIS
-
TER
BITS
(A
DDRESS
: 0000, HEX 0
X
00)
TCLKP (BIT 0)
Set to a “1”, all 7 channels will sample TPOS/TNEG
data on the rising edge of TClk. It will default to a “0”,
sampling on the falling edge.
RCLKP (BIT 1)
Set to a “1”, all channels will output RPOS/RNEG re-
ceive data on the rising edge of RClk. The default val-
ue is “0” where it will output on the falling edge.
CODE (BIT 2)
If set and if the SR/DR bit is set, will select HDB3 en-
coding for Transmit and decoding for Receive on all
channels. If CODE or SR/DR bits are “0”, AMI encod-
ing/decoding is specified.
SR/DR (BIT 3)
If set, single rail mode for the DTE side TPOS in and
RPOS out signals. RNEG is used for Line Code Vio-
lation (LCV) status. Default state is “0”, selecting du-
al-rail operation.
MUTE (BIT 4)
If set, will mute the receive outputs of a channel when
the LOS condition is detected and ARAOS is not as-
serted.
EXLOS (BIT 5)
When set, will extend the number of contiguous re-
ceived zeros to 4096 before the LOS condition is de-
clared.
ARAOS (BIT 6)
When set this bit enables insertion of “all ones data”
at RPOS/RNEG when LOS is detected on that chan-
nel.
1.4 C
HANNEL
C
ONTROL
R
EGISTERS
These registers provide a channel by channel control
of the operation and diagnostic mode of the chip. An
individual or combination of the channels can be con-
trolled. Certain combinations of modes can not be set
as pointed out in the descriptions.
LLB[6:0] (ADDRESS 0001)
Setting a bit in this register causes that channel’s
transmit input data to be sent back out of the RPOS/
RNEG receive port. The transmit data will continue to
be sent to the line unless the TAOS control is en-
abled.
RLB[6:0] (ADDRESS 0010)
Setting a bit in this register causes that channel’s re-
ceive data to be sent back out of the TTIP/TRING on
the line to the Remote end. The receive data will con-
tinue to be sent to the DTE unless the RAOS control
is enabled.
ALBX (ADDRESS 0011)
Setting a bit in this register will cause the analog sig-
nal at the output to be sent back through the receive
section to the DTE equipment. This will effectively ex-
ercise most of the internal functions of that channel.
The Analog loopback has priority over the other loop-
back modes.
TAOS[6:0] (ADDRESS 0100)
Setting this bit enables transmitting all ones data. A
Remote loopback (RLB) on the channel has priority
over this function.
RAOS[6:0] (ADDRESS 0101)
Setting this bit inserts all ones into the receive data
stream. Local loopback has priority over RAOS and
the ARAOS signal.
PDT
X[6:0] (ADDRESS 0110)
Setting this bit places the Transmit driver into a high
impedance state. Individual pin control is also avail-
able in both the Host and Hardware modes. Care
should be taken in the usage of this feature. While the
default (reset) state of this register is zero, hence en-
abling the outputs of the channel, the “PDT” pin has
T
ABLE
16: PDT
X
R
EGISTERS
- A
DDRESS
: 0110, HEX 0
X
06
B
IT
N
O
.N
AME
F
UNCTION
R
EGISTER
T
YPE
0-6 PDTx0-
PDTx6
Power-down Transmitter:
Writing a "1" to this bit shut down the transmitter channel selected and places
the TTIP/TRing driver in high impedance mode. Individual pin control is also
available to switch off the transmitter for fast redundancy application both in
Host
and
Hardware
mode.
R/W
