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XRT81L27IV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
XRT81L27
áç
áçáç
áç
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
II
RAOS[6:0] (
ADDRESS
0101) ...................................................................................................................... 18
PDTX[6:0] (
ADDRESS
0110) ....................................................................................................................... 18
2.0 The transmit section ............................................................................................................................... 19
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
. ............................................................................................................... 19
Figure 7. The Interface for the Transmission of Data From the Transmitting Terminal Equipment
to the Transmit Section of the XRT81L27 ......................................................................... 19
2.1.1 Dual-rail input mode .................................................................................................................. 19
Figure 8. Dual Rail Data from the Terminal .................................................................................... 19
2.1.2 Single-rail input mode ............................................................................................................... 19
Figure 9. Single-Rail Data From the Terminal ............................................................................... 20
2.1.3 TClk input .................................................................................................................................. 20
2.2 T
HE
E
NCODER
BLOCK
........................................................................................................................... 20
2.2.1 HDB3 Encoding ......................................................................................................................... 20
Figure 10. HDB3 Encoding .............................................................................................................. 20
2.3 T
HE
MUX
BLOCK
.................................................................................................................................. 20
2.3.1 Timing Control Block ................................................................................................................. 21
2.3.2 The Transmit Clock Duty Cycle Adjust Circuit .......................................................................... 21
2.3.3 Transmit All Ones ...................................................................................................................... 21
2.4 T
HE
P
ULSE
S
HAPING
C
IRCUIT
............................................................................................................... 21
Figure 11. ITU-T G.703 Pulse Template .......................................................................................... 22
2.5 T
HE
L
INE
D
RIVER
BLOCK
...................................................................................................................... 22
2.6 I
NTERFACING
THE
T
RANSMIT
S
ECTIONS
OF
THE
XRT81L27
TO
THE
L
INE
............................................... 22
Figure 12. Illustration of how to interface the Transmit Sections of the XRT81L27 to the Line (for
75 or 120W Applications) ................................................................................................... 23
3.0 The Receive Section ............................................................................................................................... 23
3.1 I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
TO
THE
L
INE
............................................................................... 23
Figure 13. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 75W
(Transformer-Coupled) Applications ................................................................................ 24
Figure 14. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 120W
(Transformer-Coupled) Applications ................................................................................ 24
3.2 C
APACITIVE
-C
OUPLING
THE
R
ECEIVER
TO
THE
L
INE
............................................................................... 25
Figure 15. Capacitive - Coupled Receive Sections of the XRT81L27 to the Line (for Balanced
120W Applications) ............................................................................................................. 25
3.3 T
HE
R
ECEIVE
E
QUALIZER
B
OCK
............................................................................................................ 25
3.4 T
HE
P
EAK
D
ETECTOR
AND
S
LICER
B
LOCK
............................................................................................. 26
3.5 T
HE
LOS D
ETECTOR
BLOCK
................................................................................................................. 26
Figure 16. Package Outline Drawing .............................................................................................. 27
R
EVISIONS
................................................................................................................................................. 28
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XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
3
PIN DESCRIPTIONS
N
OTE
: I -H
indicates an input pin with a 50k
Ω
pull-up Resistor, I-L indicates an input pin with a 50k
Ω
pull-down resistor.
P
IN
#N
AME
T
YPE
D
ESCRIPTION
1 RClk_0 O
Receiver 0 Clock Output
2
LOS_0 O
Receiver 0 Loss of Signal:
This signal is asserted "High" to indicate loss of signal at the receive
input.
3
RST
LBEN
I-H
Reset (Active-low): (Host Mode)
“Low” Resets the register contents to zero.
Loop-back Enable (Active-low): (Hardware Mode)
“Low” for Loop-back mode enable.
4
RTIP_0 I
Receiver 0 Bipolar Positive Input:
5
RRING_0 I
Receiver 0 Bipolar Negative Input:
6
PDTx_0 I-H
Power-down Transmitter 0:
This pin is operational for both
Host
or
Hardware Mode
.
This pin MUST be pulled “Low” to enable TTIP_0 and TRING_0 output
buffers.
Pull this pin "High" to power-down channel 0 transmitter and set TTIP_0
and TRING_0 outputs to high impedance.
7
TTIP_0 O
Transmitter 0 Tip Output:
Positive bipolar data output to the line
8
TVDD_0 Vdd
Transmitter 0 Positive Supply (3.3V± 5%)
9
TRING_0 O
Transmitter 0 Ring Output:
Negative bipolar data output to the line.
10
TGND_0 Gnd
Transmitter 0 Supply Ground
11
PDTx_2 I-H
Power-down Transmitter 2:
(see pin 6)
12
TTIP_2 O
Transmitter 2 Tip Output:
Positive bipolar data output to the line.
13
TVDD_2 Vdd
Transmitter 2 Positive Supply(3.3V± 5%)
14
TRING_2 O
Transmitter 2 Ring Output:
Negative bipolar data output to the line.
15
TGND_2 Gnd
Transmitter 2 Supply Ground.
16
AVDD AVdd
Analog Positive Supply(3.3V± 5%)
17
RTIP_2 I
Receiver 2 Bipolar Positive Input:
18
RRING_2 I
Receiver 2 Bipolar Negative Input:
19
AGND Gnd
Analog Supply Ground.
20
RTIP_4 I
Receiver 4 Bipolar Positive Input:
21
RRING_4 I
Receiver 4 Bipolar Negative Input:
22
PDTx_4 I-H
Power-down Transmitter 4:
(see pin 6)
23
TTIP_4 O
Transmitter 4 Tip Output:
Positive bipolar data output to the line.
24
TVDD_4 Vdd
Transmitter 4 Positive Supply(3.3V± 5%)
25
TRING_4 O
Transmitter 4 Ring Output:
Negative bipolar data output to the line.
XRT81L27
áç
áçáç
áç
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
4
26
TGND_4 Gnd
Transmitter 4 Supply Ground
27
PDTx_6 I-H
Power-down Transmitter 6:
(see pin 6)
28
TTIP_6 O
Transmitter 6 Tip Output:
Positive bipolar data output to the line.
29
TVDD_6 Vdd
Transmitter 6 Positive Supply(3.3V± 5%)
30
TRING_6 O
Transmitter 6 Ring Output:
Negative bipolar data output to the line.
31
TGND_6 Gnd
Transmitter 6 Supply Ground
32
MODE I-L
Mode Control Input:
This pin is used to select Hardware or Host Mode control of the device.
Tie “Low” to select
Host Mode
"High" to select
Hardware Mode
.
33
RClk_4 O
Receiver 4 Clock Output:
34
RNEG_4
LCV_4
O
Receiver 4 Negative Data Output:
In
Dual-Rail mode
, this signal is the receive n-rail output data.
Line Code Violation Output:
In
Single-Rail mode
, this signal outputs a "High" for one clock cycle to
indicate a code violation is detected in the received data.
If AMI coding is selected, every bipolar violation received will cause this
pin to go "High".
35
RPOS_4
RDATA_4
O
Receiver 4 Positive Data Output:
In
Dual-Rail mode
, this signal is the receive p-rail output data.
Receiver 4 NRZ Data Output:
In
Single-Rail mode
, this signal is the receive output data
36
LOS_4 O
Receiver 4 Loss of Signal:
(see pin 2)
37
TClk_4 I
Transmitter 4 Clock Input:
E1 rate at 2.048MHz ± 50ppm.
38
TPOS_4
TDATA_4
I
Transmitter 4 Positive Data Input:
In
Dual-Rail mode
, this signal is the p-rail input data for transmitter 4.
Transmitter 4 NRZ Data Input:
In
Single-Rail mode
, this signal is used as the NRZ input data
39
TNEG_4
CODE_4
I-L
Transmitter 4 Negative Data Input:
In
Dual-Rail mode
, this signal is the n-rail data input for transmitter 4.
In
Single-Rail mode
(pin 69=1) and with this pin tied "High", input data
at the transmit input is encoded in
HDB3
format and the substitution
code in the corresponding receive channel will be removed.
Tie this pin "Low" to enable
AMI
encoding and decoding.
40
TA O S _ 4 I - L
Transmit All Ones Channel_4:
This pin is set to insert AMI all ones data to the line using MCLK as refer-
ence.
In
Host Mode
, this pin can be left unconnected.
41
VDD Vdd
Digital Positive Supply(3.3V± 5%).
42
GND Gnd
Digital Supply Ground.
PIN DESCRIPTIONS
N
OTE
: I -H
indicates an input pin with a 50k
Ω
pull-up Resistor, I-L indicates an input pin with a 50k
Ω
pull-down resistor.
P
IN
#N
AME
T
YPE
D
ESCRIPTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

XRT81L27IV

Mfr. #:
Buy XRT81L27IV
Manufacturer:
MaxLinear
Description:
IC LIU EI 7CH 3.3V 128TQFP
Lifecycle:
New from this manufacturer.
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