13©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to V
CC
– 2V. For V
CC
= 2.5V, the V
CC
– 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5C. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
2.5V
50Ω
50Ω
R1
250
Ω
R3
250
Ω
R2
62.5
Ω
R4
62.5
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
R3
18
Ω
+
14©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 6. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
15©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
Schematic Example
Figure 7 shows an example of 853S01 application schematic. This
device can accept different types of input signal. In this example, the
input is driven by a LVPECL driver. The decoupling capacitor should
be located as close as possible to the power pin.
Figure 7. 853S01 Applications Schematic Example

853S01AGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2:1 Diff to LVPECL 150ps 490ps
Lifecycle:
New from this manufacturer.
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