4©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
Table 4D. LVPECL DC Characteristics, V
CC
= 3.3V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than V
EE
– 0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
to V
CC
– 2V.
Table 4E. LVPECL DC Characteristics, V
CC
= 2.5V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than V
EE
– 0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
to V
CC
– 2V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
PCLK0, PCLK1,
nPCLK0, nPCLK1
V
CC
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current
PCLK0, PCLK1 V
CC
= 3.465V, V
IN
= 0V -10 µA
nPCLK0, nPCLK1 V
CC
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage;
NOTE 1
150 1200 mV
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
1.2 V
CC
V
V
OH
Output High Voltage;
NOTE 3
V
CC
– 1.125 V
CC
– 0.875 V
V
OL
Output Low Voltage;
NOTE 3
V
CC
– 1.895 V
CC
– 1.62 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.495 0.975 V
V
BB
Bias Voltage 1.695 2.145 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
PCLK0, PCLK1,
nPCLK0, nPCLK1
V
CC
= V
IN
= 2.625V 150 µA
I
IL
Input Low Current
PCLK0, PCLK1 V
CC
= 2.625V, V
IN
= 0V -10 µA
nPCLK0, nPCLK1 V
CC
= 2.625V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage;
NOTE 1
150 1200 mV
V
CMR
Common Mode Input Voltage; NOTE
1, 2
1.2 V
CC
V
V
OH
Output High Voltage;
NOTE 3
V
CC
– 1.125 V
CC
– 0.875 V
V
OL
Output Low Voltage;
NOTE 3
V
CC
– 1.895 V
CC
– 1.62 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.495 0.975 V
V
BB
Bias Voltage 0.935 1.305 V
5©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V
CC
= 3.3V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 4: Driving only one input clock.
NOTE 5: Q, nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram
Table 5B. AC Characteristics, V
CC
= 2.5V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 4: Driving only one input clock.
NOTE 5: Q, nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 2.5 GHz
t
PD
Propagation Delay; NOTE 1 240 490 ps
tsk(i) Input Skew 40 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 3 150 ps
tjit
Buffer Additive Phase Jitter, RMS,
refer to Additive Phase Jitter
section; NOTE 4
622MHz, Integration Range:
12kHz - 20MHz
0.024 ps
t
R
/ t
F
Output Rise/ Fall Time 20% to 80% 100 240 ps
MUX
ISOL
MUX Isolation; NOTE 5 ƒ
OUT
622MHz 81 dB
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 2.5 GHz
t
PD
Propagation Delay; NOTE 1 240 490 ps
tsk(i) Input Skew 40 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 3 150 ps
tjit
Buffer Additive Phase Jitter, RMS,
refer to Additive Phase Jitter
section; NOTE 4
622MHz, Integration Range:
12kHz - 20MHz
0.024 ps
t
R
/ t
F
Output Rise/ Fall Time 20% to 80% 100 240 ps
MUX
ISOL
MUX Isolation; NOTE 5 ƒ
OUT
622MHz 81 dB
6©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator used is, "IFR2042 10kHz – 56.4GHz Low
Noise Signal Generator as external input to an Agilent 8133A 3GHz
Pulse Generator".
Additive Phase Jitter @ 622MHz
12kHz to 20MHz = 0.024ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)

853S01AGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2:1 Diff to LVPECL 150ps 490ps
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