16©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 853S01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 853S01 is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 26mA = 90.09mW
Power (outputs)
MAX
= 32mW/Loaded Output pair
Total Power_
MAX
(3.3V, with all outputs switching) = 90.09mW + 32mW = 122.09mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 100°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.122W * 100°C/W = 97.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance
JA
for 16 Lead TSSOP, Forced Convection
Table 6B. Thermal Resistance
JA
for 16 Lead VFQFN, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 100.0°C/W 94.2°C/W 90.2°C/W
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W
17©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
The LVPECL output driver circuit and termination are shown in Figure 8.
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CC
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.875V
(V
CC_MAX
– V
OH_MAX
) = 0.875V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.62V
(V
CC_MAX
– V
OL_MAX
) = 1.62V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.875V)/50] * 0.875V = 19.691mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L]
* (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.62V)/50] * 1.62V = 12.31mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω
18©2016 Integrated Device Technology, Inc. Revision B, March 4, 2016
853S01 Datasheet
Reliability Information
Table 7A.
JA
vs. Air Flow Table for a 16 Lead VFQFN
Table 7B.
JA
vs. Air Flow Table for an 16 Lead TSSOP Forced Convection
Transistor Count
The transistor count for 853S01 is: 244
This device is pin and function compatible and a suggested replacement for ICS85301.
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 100.0°C/W 94.2°C/W 90.2°C/W

853S01AGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2:1 Diff to LVPECL 150ps 490ps
Lifecycle:
New from this manufacturer.
Delivery:
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