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NCP1063AP060G

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NCP1060, NCP1063
www.onsemi.com
16
Application Information
Startup Sequence
When the power supply is first powered from the mains
outlet, the internal current source (typically 8.0 mA) is
biased and charges up the V
CC
capacitor from the drain pin.
Once the voltage on this V
CC
capacitor reaches the V
CC(on)
level (typically 9.0 V), the current source turns off and
pulses are delivered by the output stage: the circuit is awake
and activates the power MOSFET if the bulk voltage is
above V
HV(EN)
level (87 V typically) for A version and if
bulk voltage is above V
start(min)
(21 V dc) for B version.
Figure 30 details the simplified internal circuitry.
+−
V
CC(on)
V
CC(min)
I
start1
Vbulk
5
8
1
C
VCC
R
limit
I1
I
CC1
I2
VCC > 18V ?
à
OVP fault
Drain
+−
V
OVP
Figure 30. The Internal Arrangement of the Start−up Circuitry
Being loaded by the circuit consumption, the voltage on
the V
CC
capacitor goes down. When V
CC
is below V
CC(min)
level (7.5 V typically), it activates the internal current source
to bring V
CC
toward V
CC(on)
level and stops again: a cycle
takes place whose low frequency depends on the V
CC
capacitor and the IC consumption. A 1.5 V ripple takes place
on the V
CC
pin whose average value equals (V
CC(on)
+
V
CC(min)
)/2. Figure 31 portrays a typical operation of the
DSS.
NCP1060, NCP1063
www.onsemi.com
17
0
1
2
3
4
5
6
7
8
9
10
012345678910
V
CC
9.0 V
V
CCTH
Startup Duration
Figure 31. The Charge/Discharge Cycle Over a 1 mF V
CC
Capacitor
Device
Internal
Pulses
7.5 V
TIME (ms)
V (V)
As one can see, even if there is auxiliary winding to provide
energy for V
CC
, it happens that the device is still biased by
DSS during start−up time or some fault mode when the
voltage on auxiliary winding is not ready yet. The V
CC
capacitor shall be dimensioned to avoid V
CC
crosses V
CC(off)
level, which stops operation. The ΔV between V
CC(min)
and
V
CC(off)
is 0.5 V. There is no current source to charge V
CC
capacitor when driver is on, i.e. drain voltage is close to zero.
Hence the V
CC
capacitor can be calculated using
C
VCC
w
I
CC1
@ D
max
f
OSC
@ DV
(eq. 1)
Take the 60 kHz device as an example. C
VCC
should be
above
0.8 m @ 72%
54 kHz @ 0.5
+ 21 nF.
A margin that covers the temperature drift and the voltage
drop due to switching inside FET should be considered, and
thus a capacitor above 0.1 mF is appropriate.
The V
CC
capacitor has only a supply role and its value
does not impact other parameters such as fault duration or
the frequency sweep period for instance. As one can see on
Figure 30, an internal OVP comparator, protects the
switcher against lethal V
CC
runaways. This situation can
occur if the feedback loop optocoupler fails, for instance,
and you would like to protect the converter against an over
voltage event. In that case, the over voltage protection
(OVP) circuit and immediately stops the output pulses for
t
recovery
duration (400 ms typically). Then a new start−up
attempt takes place to check whether the fault has
disappeared or not. The OVP paragraph gives more design
details on this particular section.
Fault Condition – Short−circuit on V
CC
In some fault situations, a short−circuit can purposely
occur between V
CC
and GND. In high line conditions (V
HV
= 370 V
DC
) the current delivered by the startup device will
seriously increase the junction temperature. For instance,
since I
start1
equals 5 mA (the min corresponds to the highest
T
j
), the device would dissipate 370 x 5 m = 1.85 W. To avoid
this situation, the controller includes a novel circuitry made
of two startup levels, I
start1
and I
start2
. At power−up, as long
as V
CC
is below a 1.4 V level, the source delivers I
start2
(around 500 mA typical), then, when V
CC
reaches 1.4 V, the
source smoothly transitions to I
start1
and delivers its nominal
value. As a result, in case of short−circuit between V
CC
and
GND, the power dissipation will drop to 370 x 500 m =
185 mW. Figure 31 portrays this particular behavior.
The first startup period is calculated by the formula C x V
= I x t, which implies a 1 m x 1.4 / 500 m = 2.8 ms startup time
for the first sequence. The second sequence is obtained by
toggling the source to 8 mA with a delta V of V
CC(on)
–
V
CCTH
= 9.0 – 1.4 = 7.6 V, which finally leads to a second
startup time of 1 m x 7.6 / 8 m = 0.95 ms. The total startup
time becomes 2.8 m + 0.95 m = 3.75 ms. Please note that this
calculation is approximated by the presence of the knee in
the vicinity of the transition.
NCP1060, NCP1063
www.onsemi.com
18
Fault Condition – Output Short−circuit
As soon as V
CC
reaches V
CC(on)
, drive pulses are
internally enabled. If everything is correct, the auxiliary
winding increases the voltage on the V
CC
pin as the output
voltage rises. During the start−sequence, the controller
smoothly ramps up the peak drain current to maximum
setting, i.e. I
IPK
, which is reached after a typical period of
4 ms. When the output voltage is not regulated, the current
coming through COMP pin is below I
COMPfault
level (40 mA
typically), which is not only during the startup period but
also anytime an overload occurs, an internal error flag is
asserted, Ipflag, indicating that the system has reached its
maximum current limit set point. The assertion of this flag
triggers a fault counter t
SCP
(48 ms typically). If at counter
completion, I
pflag
remains asserted, all driving pulses are
stopped and the part stays off in t
recovery
duration (about
400 ms). A new attempt to re−start occurs and will last
48 ms providing the fault is still present. If the fault still
affects the output, a safe burst mode is entered, affected by
a low duty−cycle operation (11%). When the fault
disappears, the power supply quickly resumes operation.
Figure 32 depicts this particular mode:
Figure 32. In case of short−circuit or overload, the NCP106X protects itself and the power supply via a low
frequency burst mode. The V
CC
is maintained by the current source and self−supplies the controller.
IpFlag
Timer
DRV
internal
48 ms typ.
400 ms typ.
Fault
Open loop FB
V
CC(on)
V
CC(min)
V
CC
V
COMP
Auto−recovery Over Voltage Protection
The particular NCP106X arrangement offers a simple
way to prevent output voltage runaway when the
optocoupler fails. As Figure 33 shows, a comparator
monitors the V
CC
pin. If the auxiliary pushes too much
voltage into the C
VCC
capacitor, then the controller
considers an OVP situation and stops the internal drivers.
When an OVP occurs, all switching pulses are permanently
disabled. After t
recovery
delay, it resumes the internal drivers.
If the failure symptom still exists, e.g. feedback
opto−coupler fails, the device keeps the auto−recovery OVP
mode. It is recommended insertion of a resistor (
R
limit
)
between the auxiliary dc level and the V
CC
pin to protect the
IC against high voltage spikes, which can damage the IC,
and to filter out the Vcc line to avoid undesired OVP
activation. R
limit
should be carefully selected to avoid
triggering the OVP as we discussed, but also to avoid
disturbing the V
CC
in low / light load conditions.
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (V
nom
), this voltage can drop below 10 V
(V
stby
) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency re−fueling rate of the V
CC
capacitor is not
enough to keep a proper auxiliary voltage.
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NCP1063AP060G

Mfr. #:
Buy NCP1063AP060G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers HV SWITCHER FOR LOW POWER
Lifecycle:
New from this manufacturer.
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