9FG1901HKLF Datasheet 9FG1901HKLF | P1-P3

Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

Recommended Application:

DB1900G: CPU Host Bus, PCI Express and Fully-Buffered

DIMM clocking

Features:

• Power up default is all outputs in 1:1 mode

• DIF_(16:0) can be “gear-shifted” from the input CPU

Host Clock

• DIF_(18:17) can be “gear-shifted” from the input CPU

Host Clock

• Spread spectrum compatible

• Supports output clock frequencies up to 400 MHz

• 8 Selectable SMBus addresses

• SMBus address determines PLL or Bypass mode

• VDDA controlled power down mode

Key Specifications:

• DIF output cycle-to-cycle jitter < 50ps

• DIF (0:18) output-to-output skew < 225ps

• DIF (0:16) output-to-output skew < 100ps

Frequency Generator for P4

™™

™

CPU, PCI Express

™™

™

& Fully Buffered DIMM Clocks

Other names and brands may be claimed as the property of others.

Power Down Functionality

Pin Configuration

72-pin MLF

Functionality at Power Up (PLL Mode)

SMB_A2_PLLBYP#

CLK_IN#

CLK_IN

OE17_18#

DIF_18#

DIF_18

DIF_17#

DIF_17

GND

VDD

DIF_16#

DIF_16

OE16#

DIF_15#

DIF_15

OE15#

DIF_14#

DIF_14

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

IREF 1 54 OE14#

GNDA 2 53 DIF_13#

VDDA/PD# 3 52 DIF_13

HIGH_BW# 4 51 OE13#

FS_A_410 5 50 DIF_12#

DIF_0 6 49 DIF_12

DIF_0# 7 48 OE12#

DIF_1 8 47

VDD

DIF_1# 9 46

GND

GND 10 45 DIF_11#

VDD 11 44 DIF_11

DIF_2 12 43 OE11#

DIF_2# 13 42 DIF_10#

DIF_3 14 41 DIF_10

DIF_3# 15 40 OE10#

DIF_4 16 39 DIF_9#

DIF_4# 17 38 DIF_9

OE_01234# 18 37 OE9#

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

SMBCLK

SMBDAT

OE5#

DIF_5

DIF_5#

OE6#

DIF_6

DIF_6#

VDD

GND

OE7#

DIF_7

DIF_7#

OE8#

DIF_8

DIF_8#

SMB_A0

SMB_A1

ICS9FG1901

FS_A_410

CLK_IN (CPU FSB)

MHz

DIF_(18:0)

MHz

1 100 <= CLK_IN < 200 CLK_IN

0 200<= CLK_IN <= 400 CLK_IN

1. FS_A_410 is a low-threshold input. Please see the V

IL_FS

and V

IH_FS

specifications in the Input/Supply/Common Output Parameters Table for

correct values.

VDDA/PD# CLK_IN/CLK_IN# DIF DIF#

3.3V (NOM) Running ON

GND X

OFF

Functionality Note

It is recommended that Byte 2, bit 6 be toggled from 1 to 0

and back to 1, the first time VDDA is applied. This ensures

proper initialization of the device.

Hi-Z

INPUTS OUTPUTS

PLL State

Running

Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

Pin Description

PIN # PIN NAME PIN TYPE DESCRIPTION

1 IREF OUT

This pin establishes the reference current for the differential current-mode output

pairs. This pin requires a fixed precision resistor tied to ground in order to

establish the appropriate current. 475 ohms is the standard value.

2 GNDA PWR Ground pin for the PLL core.

3 VDDA/PD# PWR

3.3V power for the PLL core that also functions as Power Down. Collapsing this

power supply places the device in Power Down mode.

4HIGH_BW# IN

3.3V input for selecting PLL Band Width

0 = Hi

h, 1= Low

5FS_A_410 IN

3.3V tolerant low threshold input for CPU frequency selection. This pin requires

CK410 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS

threshold values.

6 DIF_0 OUT 0.7V differential true clock output

7 DIF_0# OUT 0.7V differential complement clock output

8 DIF_1 OUT 0.7V differential true clock output

9 DIF_1# OUT 0.7V differential complement clock output

10 GND PWR Ground pin.

11 VDD PWR Power suppl

, nominal 3.3V

12 DIF_2 OUT 0.7V differential true clock output

13 DIF_2# OUT 0.7V differential complement clock output

14 DIF_3 OUT 0.7V differential true clock output

15 DIF_3# OUT 0.7V differential complement clock output

16 DIF_4 OUT 0.7V differential true clock output

17 DIF_4# OUT 0.7V differential complement clock output

18 OE_01234# IN

Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.

1 = tri-state outputs, 0 = enable outputs

19 SMBCLK IN Clock pin of SMBUS circuitr

, 5V tolerant

20 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant

21 OE5# IN

Active low input for enabling DIF pair 5.

1 = tri-state outputs, 0 = enable outputs

22 DIF_5 OUT 0.7V differential true clock output

23 DIF_5# OUT 0.7V differential complement clock output

24 OE6# IN

Active low input for enabling DIF pair 6.

1 = tri-state outputs, 0 = enable outputs

25 DIF_6 OUT 0.7V differential true clock output

26 DIF_6# OUT 0.7V differential complement clock output

27 VDD PWR Power supply, nominal 3.3V

28 GND PWR Ground pin.

29 OE7# IN

Active low input for enabling DIF pair 7.

1 = tri-state outputs, 0 = enable outputs

30 DIF_7 OUT 0.7V differential true clock output

31 DIF_7# OUT 0.7V differential complement clock output

32 OE8# IN

Active low input for enabling DIF pair 8.

1 = tri-state outputs, 0 = enable outputs

33 DIF_8 OUT 0.7V differential true clock output

34 DIF_8# OUT 0.7V differential complement clock output

35 SMB_A0 IN SMBus address bit 0 (LSB)

36 SMB_A1 IN SMBus address bit 1

Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

Pin Description (Continued)

PIN # PIN NAME PIN TYPE DESCRIPTION

37 OE9# IN

Active low input for enabling DIF pair 9.

1 = tri-state outputs, 0 = enable outputs

38 DIF_9 OUT 0.7V differential true clock output

39 DIF_9# OUT 0.7V differential complement clock output

40 OE10# IN

Active low input for enabling DIF pair 10.

1 = tri-state outputs, 0 = enable outputs

41 DIF_10 OUT 0.7V differential true clock output

42 DIF_10# OUT 0.7V differential complement clock output

43 OE11# IN

Active low input for enabling DIF pair 11.

1 = tri-state outputs, 0 = enable outputs

44 DIF_11 OUT 0.7V differential true clock output

45 DIF_11# OUT 0.7V differential complement clock output

46 GND PWR Ground pin.

47 VDD PWR Power suppl

, nominal 3.3V

48 OE12# IN

Active low input for enabling DIF pair 12.

1 = tri-state outputs, 0 = enable outputs

49 DIF_12 OUT 0.7V differential true clock output

50 DIF_12# OUT 0.7V differential complement clock output

51 OE13# IN

Active low input for enabling DIF pair 13.

1 = tri-state outputs, 0 = enable outputs

52 DIF_13 OUT 0.7V differential true clock output

53 DIF_13# OUT 0.7V differential complement clock output

54 OE14# IN

Active low input for enabling DIF pair 14.

1 = tri-state outputs, 0 = enable outputs

55 DIF_14 OUT 0.7V differential true clock output

56 DIF_14# OUT 0.7V differential complement clock output

57 OE15# IN

Active low input for enabling DIF pair 15.

1 = tri-state outputs, 0 = enable outputs

58 DIF_15 OUT 0.7V differential true clock output

59 DIF_15# OUT 0.7V differential complement clock output

60 OE16# IN

Active low input for enabling DIF pair 16.

1 = tri-state outputs, 0 = enable outputs

61 DIF_16 OUT 0.7V differential true clock output

62 DIF_16# OUT 0.7V differential complement clock output

63 VDD PWR Power suppl

, nominal 3.3V

64 GND PWR Ground pin.

65 DIF_17 OUT 0.7V differential true clock output

66 DIF_17# OUT 0.7V differential complement clock output

67 DIF_18 OUT 0.7V differential true clock output

68 DIF_18# OUT 0.7V differential complement clock output

69 OE17_18# IN

Active low input for enabling DIF pairs 17 and 18.

1 = tri-state outputs, 0 = enable outputs

70 CLK_IN IN Input for reference clock.

71 CLK_IN# IN "Complementary" reference clock input.

72 SMB_A2_PLLBYP# IN

SMBus address bit 2. When Low, the part operates as a fanout buffer with the

PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with

the PLL operating.

0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

9FG1901HKLF

Mfr. #:

Buy 9FG1901HKLF

Manufacturer:

Description:

Clock Buffer PCIE BUFFER

Lifecycle:

New from this manufacturer.

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