7
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2, R
P
=49.9Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output Impedance
Zo
1
V
O
= V
x
3000
1
Voltage High VHigh 660 750 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
e Vovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
Volta
e
abs
Vcross
(
abs
)
250 550 mV 1
Crossin
g
Volta
g
e
(
var
)
d-Vcross Variation of crossin
g
over all ed
g
es 140 mV 1
Lon
g
Accurac
y
pp
msee T
p
eriod min-max values -300 300
pp
m1,2
400MHz nominal 2.4993 2.5008 ns 2
400MHz s
p
read 2.4993 2.5133 ns 2
333.33MHz nominal 2.9991 3.0009 ns 2
333.33MHz s
p
read 2.9991 3.016 ns 2
266.66MHz nominal 3.7489 3.7511 ns 2
266.66MHz s
p
read 3.7489 3.77 ns 2
200MHz nominal 4.9985 5.0015 ns 2
200MHz s
p
read 4.9985 5.0266 ns 2
166.66MHz nominal 5.9982 6.0018 ns 2
166.66MHz s
p
read 5.9982 6.0320 ns 2
133.33MHz nominal 7.4978 7.5023 ns 2
133.33MHz s
p
read 7.4978 7.5400 ns 2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz s
p
read 9.9970 10.0533 ns 2
400MHz nominal/s
p
read 2.4143 ns 1,2
333.33MHz nominal/s
p
read 2.9141 ns 1,2
266.66MHz nominal/s
p
read 3.6639 ns 1,2
200MHz nominal/s
p
read 4.8735 ns 1,2
166.66MHz nominal/s
p
read 5.8732 ns 1,2
133.33MHz nominal/s
p
read 7.3728 ns 1,2
100.00MHz nominal/s
p
read 9.8720 ns 1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175 400 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 425 700 ps 1
Rise Time Variation
d-t
r
20 125 ps 1
Fall Time Variation
d-t
f
15 125 ps 1
Duty Cycle
d
t3
Measurement from differential wavefrom 45 50.5 55 % 1
Output-to-Output Skew - DIF(0:16)
t
sk3_016
V
T
= 50%, Skew within Group of 17, 1
to 1 mode onl
y
75 100 ps 1
Output-to-Output Skew - DIF(0:18)
t
sk3_018
V
T
= 50%, Skew across all outputs 1 to
1 mode onl
y
200 225 ps 1
t
pdpll
PLL Mode -500 500 ps 1
t
pdbyp
Bypass Mode 2.5 3.6 4.5 ns 1
PLL mode,
from differential wavefrom
40 50 ps 1
Bypass mode as additive jitter 25 50 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410 accuracy requirements
T
absmin
Absolute min period
mV
Measurement on single ended signal
using absolute value.
mV
Jitter, Cycle to cycle
t
jcyc-cyc
Average period Tperiod
Input-to-Output Delay
Statistical measurement on sin
g
le ended
signal using oscilloscope math function.
8
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
PLL Bandwidth and Peaking
Parameter Conditions Min Typical Max Units Notes
PLL Jitter Peaking j
peak-hibw
(HIGH_BW# = 0) 0 1 2.5 dB 2,8
PLL Jitter Peaking j
peak-lobw
(HIGH_BW# = 1) 0 1 2 dB 2,8
PLL Bandwidth pll
HIBW
(HIGH_BW# = 0) 2 2.3 4 MHz 1,8
PLL Bandwidth pll
LOBW
(HIGH_BW# = 1) 0.7 1.28 1.4 MHz 1,8
Output phase jitter impact – PCIe*
Gen1
θ
PCIe1
(including PLL BW 1.5-22 MHz, z = 0. 54,
Td=10 ns, Ftrk=1.5 MHz )
0 77 108 ps 3,6,7,8
Output phase jitter impact – FBD
θ
FBD
(including PLL BW 11- 33 Mz, z = 0.54,
Td=5 ns, Ftrk=0.2 MHz)
0 3 ps RMS 3,4,7,8
NOTES:
1.
Measured at 3 db down or half power point.
2.
Measured as maximum pass band gain. At frequencies within the loop BW , highest point of magnification is called PLL jitter peaking.
3.
Post processed evaluation through Intel supplied Matlab sc ripts.
4.
Refer to FB-DIMM Specification: “High Speed Differential Point-to-Point Link at 1.5 V” for updates to this specification.
6.
These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be ex trapolated to this BER target.
7.
z = 0.54 is implying a jitter peaking of 3 dB.
8. Guaranteed by design and characterization, not 100% tested in production.
5.
PCIe* Gen2 filter characteristics are subject to final ratification by PC ISIG. Please check the PCI* SIG for the latest specification. Tested with DBxx00G driven by low phase
nois e signal generator such as an Agilent 8133A.
9
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
9FG1901 SMBus Address Mapping
when using CK410/CK410B, 9FG1201, and
9DB104/108
SMB Adr: DC
9DB104/108
(DB400/800)
SMB Adr: D2
954101
932S401
(CK410/410B)
PLL BYPASS MODE
SMB_A2_PLLBYP# = 0
P
L
L
Z
D
B
M
O
D
E
S
M
B
_
A
2
_
P
L
L
B
Y
P
#
=
1
SMB_A(2:0) = 100
SMB Adr: D8
SMB_A(2:0) = 101
SMB Adr: DA
SMB_A(2:0) = 110
SMB Adr: DC
SMB_A(2:0) = 111
SMB Adr: DE
SMB_A(2:0) = 000
SMB Adr: D0
9FG1901
(DB1900G)
SMB_A(2:0) = 001
SMB Adr: D2
SMB_A(2:0) = 010
SMB Adr: D4
SMB_A(2:0) = 011
SMB Adr: D6
9FG1901
(DB1900G)
9FG1901
(DB1900G)
9FG1901
(DB1900G)
9FG1901
(DB1900G)
9FG1901
(DB1900G)
9FG1901
(DB1900G)
9FG1901
(DB1900G)
SMB_A(2:0) = 100
SMB Adr: D8
9FG1201/2
(DB1200G)
SMB_A(2:0) = 101
SMB Adr: DA
9FG1201/2
(DB1200G)
SMB_A(2:0) = 110
SMB Adr: DC
9FG1201/2
(DB1200G)
SMB_A(2:0) = 111
SMB Adr: DE
9FG1201/2
(DB1200G)
SMB_A(2:0) = 000
SMB Adr: D0
9FG1201/2
(DB1200G)
SMB_A(2:0) = 001
SMB Adr: D2
9FG1201/2
(DB1200G)
SMB_A(2:0) = 010
SMB Adr: D4
9FG1201/2
(DB1200G)
SMB_A(2:0) = 011
SMB Adr: D6
9FG1201/2
(DB1200G)
OR
OR
OR
OR
OR
OR
OR
OR
OR
OR

9FG1901HKLF

Mfr. #:
Manufacturer:
Description:
Clock Buffer PCIE BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet