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9FG1901HKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
10
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
SMBusTable: FSB Frequency Select Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
GRSEL_17 Group of 17 gear ratio select RW Gear Ratio 1:1
1
Bit 6
GRSEL_2 Group of 2 gear ratio select RW Gear Ratio 1:1
1
Bit 5
X
Bit 4
RW Latch
Bit 3
FSBG_3 FSB Gear Ratio FS_3 RW x
Bit 2
FSBG_2 FSB Gear Ratio FS_2 RW 0
Bit 1
FSBG_1 FSB Gear Ratio FS_1 RW x
Bit 0
FSBG_0 FSB Gear Ratio FS_0 RW 1
SMBusTable: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
DIF_7 Output Control RW Hi-Z Enable 1
Bit 6
DIF_6 Output Control RW Hi-Z Enable 1
Bit 5
DIF_5 Output Control RW Hi-Z Enable 1
Bit 4
DIF_4 Output Control RW Hi-Z Enable 1
Bit 3
DIF_3 Output Control RW Hi-Z Enable 1
Bit 2
DIF_2 Output Control RW Hi-Z Enable 1
Bit 1
DIF_1 Output Control RW Hi-Z Enable 1
Bit 0
DIF_0 Output Control RW Hi-Z Enable 1
SMBusTable: Output and PLL BW Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
RW High BW Low BW
1
Bit 6
RW Bypass PLL
1
Bit 5
DIF_13 Output Control RW Hi-Z Enable 1
Bit 4
DIF_12 Output Control RW Hi-Z Enable 1
Bit 3
DIF_11 Output Control RW Hi-Z Enable 1
Bit 2
DIF_10 Output Control RW Hi-Z Enable 1
Bit 1
DIF_9 Output Control RW Hi-Z Enable 1
Bit 0
DIF_8 Output Control RW Hi-Z Enable 1
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
R X
Bit 6
R X
Bit 5
R X
Bit 4
R X
Bit 3
R X
Bit 2
R X
Bit 1
R X
Bit 0
R X
Readback
Readback
Readback
Readback
Readback - OE5# Input
Readback - OE6# Input
Readback - OE_01234# Input
Readback
Readback
see note PLL_BW# adjust
Readback - OE7# Input
8
-
-
B
y
te 1
B
y
te 0
DIF(16:0)
DIF(18:17)
FS_A_410 Latched Input-
Reserved
See ICS9FG1901
Programmable Gear Ratios
Table
-
-
72
Readback - OE9# Input
Readback - OE8# Input
see note BYPASS# test mode / PLL
B
y
te 3
B
y
te 2
Readback - SMB_A2_PLLBYP# In Readback
Readback - HIGH_BW# In Readback
11
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
SMBusTable: Output Enable Readback Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
R X
Bit 6
R X
Bit 5
R X
Bit 4
R X
Bit 3
R X
Bit 2
R X
Bit 1
R X
Bit 0
R X
SMBusTable: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
RID3 R - - X
Bit 6
RID2 R - - X
Bit 5
RID1 R - - X
Bit 4
RID0 R - - X
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
SMBusTable: DEVICE ID
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
RW 1
Bit 6
RW 0
Bit 5
RW 0
Bit 4
RW 1
Bit 3
RW 0
Bit 2
RW 0
Bit 1
RW 0
Bit 0
RW 1
SMBusTable: Byte Count Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5
BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3
BC3 RW - - 0
Bit 2
BC2 RW - - 1
Bit 1
BC1 RW - - 1
Bit 0
BC0 RW - - 1
54
51
48
43
40
-
Readback - OE17_18# Input Readback
Device ID 2 Reserved
Device ID 1 Reserved
69
57
Readback
Readback
Readback
Readback
Device ID 3
Device ID 0
Writing to this register
configures how many bytes
will be read back.
-
-
-
-
-
-
-
-
-
-
-
-
Device ID 4
-
Reserved
Readback - OE14# Input Readback
Readback - OE10# Input
Device ID 5 Reserved
-
-
B
y
te 7
-
-
-
-
-
-
-
B
y
te 5
-
B
y
te 6
60
B
y
te 4
Readback
Readback - OE15# Input Readback
Reserved
Reserved
REVISION ID
ReservedDevice ID 6
Reserved
Readback - OE13# Input
Readback - OE16# Input
Device ID 7 (MSB)
Readback - OE12# Input
VENDOR ID
Readback - OE11# Input
12
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
SMBusTable: Control Pin Readback Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
R X
Bit 6
X
Bit 5
X
Bit 4
DIF_18 Output Control RW Hi-Z Enable 1
Bit 3
DIF_17 Output Control RW Hi-Z Enable 1
Bit 2
DIF_16 Output Control RW Hi-Z Enable 1
Bit 1
DIF_15 Output Control RW Hi-Z Enable 1
Bit 0
DIF_14 Output Control RW Hi-Z Enable 1
SMBusTable: Reserved Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: M/N Programming & Watchdog Safe Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
M/N_EN
Gearing PLL and 1:1 PLL M/N
Programming Enable
RW Disable Enable 0
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Gearing PLL Frequency Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
Gearing PLL N Div8 N Divider Prog bit 8 RW X
Bit 6
Gearing PLL N Div9 N Divider Prog bit 9 RW X
Bit 5
Gearing PLL M Div5 RW X
Bit 4
Gearing PLL M Div4 RW X
Bit 3
Gearing PLL M Div3 RW X
Bit 2
Gearing PLL M Div2 RW X
Bit 1
Gearing PLL M Div1 RW X
Bit 0
Gearing PLL M Div0 RW X
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
B
y
te 9
B
y
te 8
RESERVED
-
-
M Divider Programming
bit (5:0)
-
-
-
-
-
B
y
te 11
-
B
y
te 10
-
RESERVED
5 Readback - FS_A_410 Readback
RESERVED
RESERVED
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9FG1901HKLF

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Buy 9FG1901HKLF
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Description:
Clock Buffer PCIE BUFFER
Lifecycle:
New from this manufacturer.
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