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9FG1901HKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
Block Diagram
Power Groups
The ICS9FG1901 follows the Intel DB1900G Differential Buffer Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410 or CK410B main clock
generator, such as the ICS954101 or ICS932S401, drives the ICS9FG1901. The ICS9FG1901 can provide outputs up to
400MHz.
General Description
STOP
LOGIC
CLK_IN
CLK_IN#
DIF(16:0)
CONTROL
LOGIC
HIGH_BW#
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
17
IREF
OE(16:5)#,
OE_01234#
13
SMB_A0
SMB_A1
FS_A_410
STOP
LOGIC
DIF(18:17)
2
OE_17_18#
GEAR
SHIFT
LOGIC
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
VDD GND
3 2 Main PLL, Analog
11,27,47,63 10,28,46,64 DIF clocks
Description
Pin Number
5
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
ICS9FG1901 Programmable Gear Ratios
Bit 3
Bit 2
Bit 1
Bit 0
200.0 266.7 320.0 333.3 400.0
00000 3 1 0.333 66.7 88.9 106.7 111.1 133.3
00001 5 2 0.400 80.0106.7 128.0 133.3 160.0
00010 12 5 0.417 83.3111.1 133.3 138.9 166.7
00011 2 1 0.500 100.0133.3 160.0 166.7 200.0
00100 5 3 0.600 120.0160.0 192.0 200.0 240.0
00101 8 5 0.625 125.0166.7 200.0 208.3 250.0
00110 3 2 0.667 133.3177.8 213.3 222.2 266.7
00111 4 3 0.750 150.0200.0 240.0 250.0 300.0
01000 6 5 0.833 166.7222.2 266.7 277.8 333.3
0
1 0 0 1 1 1 1.000 200.0 266.7 320.0 333.3 400.0
01010 5 6 1.200 240.0320.0 384.0 400.0 NA
01011 4 5 1.250 250.0333.3 400.0 NA NA
01100 3 4 1.333 266.7355.6 NA NA NA
01101 2 3 1.500 300.0400.0 NA NA NA
01110 3 5 1.667 333.3 NA NA NA NA
01111 1 2 2.000 400.0 NA NA NA NA
100 133.33 160 166.67
10000 3 1 0.333
10001 5 2 0.400 NA 53.3 64.0 66.7
10010 12 5 0.417 NA 55.6 66.7 69.4
10011 2 1 0.500 50.0 66.7 80.0 83.3
10100 5 3 0.600 60.0 80.0 96.0 100.0
10101 8 5 0.625 62.5 83.3 100.0 104.2
10110 3 2 0.667 66.7 88.9 106.7 111.1
10111 5 4 0.800 80.0106.7 128.0 133.3
11000 6 5 0.833 NA 111.1 133.3 138.9
1
1 0 0 1 1 1 1.000 100.0 133.3 160.0 166.7
11010 5 6 1.200 120.0160.0 192.0 200.0
11011 4 5 1.250 125.0166.7 200.0 208.3
11100 3 4 1.333 133.3177.8 213.3 222.2
11101 2 3 1.500 150.0200.0
11110 3 5 1.667 166.7222.2 266.7 277.8
11111 1 2 2.000 200.0266.7 320.0 333.3
Shaded areas are shown for reference only and are not necessarily valid operating points
FS_A_410
Input (CPU FSB) and Output
Frequencies (MHz)
Input
(m)
Output
(n)
Gear Ratio
(n/m)
SMBus
Byte 0
Note: Lines in
BOLD
are Power-up defaults for FS_A_410 = 0 and 1 respectively.
CLK IN
(
CPU FSB
)
Fre
q
uenc
y
(
MHz
)
6
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
Absolute Max
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage V
DD
+ 0.5V V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 V
DD
+ 0.5V V
Ts Storage Temperature -65 150
°
C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model 2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V
Input High Current I
IH
V
IN
= V
DD
-5 5 uA
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V
Low Threshold Input-
Low Volta
g
e
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V
Operating Current I
DD3.3OP
all outputs driven
450
600 mA
Powerdown Current I
DD3.3PD
all differential pairs tri-stated
13
36 mA
Input Frequency F
i
V
DD
= 3.3 V 100 400 MHz 3
Pin Inductance L
pin
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 2.500 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up or valid input
clock, whichever comes last
1.300 1.8 ms 1,2
Modulation Frequency
Tracking
Triangular Modulation 30 33 kHz 1
SMBus Voltage V
MAX
Maximum input voltage 5.5 V 1
Low-level Output Voltage V
OL
@ I
PULLUP
0.4 V 1
Current sinking at
V
OL
= 0.4 V
I
PULLUP
4mA1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Out
p
ut fre
q
uenc
y
accurac
y
is de
p
endent u
p
on the accurac
y
of the in
p
ut fre
q
uenc
y
measured at the CLK_IN
p
ins.
Input Low Current
Input Capacitance
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9FG1901HKLF

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Buy 9FG1901HKLF
Manufacturer:
Description:
Clock Buffer PCIE BUFFER
Lifecycle:
New from this manufacturer.
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