16
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
A1 0 0.05
A3
b 0.18 0.3
e
0.25 Reference
0.50 BASIC
DIMENSIONS
SYMBOL
N
D
N
E
D x E BASIC
D2 MIN. / MAX.
E2 MIN. / MAX.
L MIN. / MAX.
ICS 72L
TOLERANCE
N
72
18
18
DIMENSIONS
Reference: JEDEC Publication 95, MO-220
10.00 x 10.00
A 0.8
1.0
SYMBOL
MIN.
MAX.
5.75 / 6.15
5.75 / 6.15
0.3 / 0.5
Ordering Information
ICS9FG1901yKLF-T
Example:
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y K - LF T
17
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
Revision History
Rev. Issue Date Description Page #
A 4/25/2005
1. Added Symbol "A" to Dimensions table.
2. Preliminary Release.
15
B 12/19/2005 1. Rearranged page 1 to enlarge Pin Configuration 1
C 6/14/2006
1. Updated TBD to actual values.
2. Added PLL BW and Peaking Table.
3. Updated Skew specs.
4. Updated Paddle Dimensions. Various
D 8/17/2006 Final Release. -
E 1/2/2007
1. Added Output Dividers to Bytes 13 and 19 for Rev H
devices.
2. Changed PLL1 and PLL2 naming to 1:1 and Gearing PLL
Various

9FG1901HKLF

Mfr. #:
Manufacturer:
Description:
Clock Buffer PCIE BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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