Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
50
Interrupt Priority Structure
The P89C660/662/664/668 has an 8 source four-level interrupt
structure (see Table 13).
There are 4 SFRs associated with the four-level interrupt. They are
the IE, IP, IEN1, and IPH (see Figures 35, 36, 37, and 38). The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible. The IPH is located at SFR address B7H. The
structure of the IPH register and a description of its bits is shown in
Figure 37.
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
IPH.x IP.x
0 0 Level 0 (lowest priority)
0 1 Level 1
1 0 Level 2
1 1 Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except that there are four interrupt levels rather than
two (as on the 80C51). An interrupt will be serviced as long as an
interrupt of equal or higher priority is not already being serviced. If
an interrupt of equal or higher level priority is being serviced, the
new interrupt will wait until it is finished before being serviced. If a
lower priority level interrupt is being serviced, it will be stopped and
the new interrupt serviced. When the new interrupt is finished, the
lower priority level interrupt that was stopped will be completed.
Table 13. Interrupt Table
SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? VECTOR ADDRESS
X0 1 IE0 N (L)
1
Y (T)
2
03H
SI01 (I
2
C) 2 — N 2BH
T0 3 TP0 Y 0BH
X1 4 IE1 N (L) Y (T) 13H
T1 5 TF1 Y 1BH
SP 6 RI, TI N 23H
T2 7 TF2, EXF2 N 3BH
PCA 8 CF, CCFn
n = 0–4
N 33H
NOTES:
1. L = Level activated
2. T = Transition activated
EX0IEN0 (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT SYMBOL FUNCTION
IEN0.7 EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IEN0.6 EC PCA interrupt enable bit
IEN0.5 ES1 I
2
C interrupt enable bit.
IEN0.4 ES0 Serial Port interrupt enable bit.
IEN0.3 ET1 Timer 1 interrupt enable bit.
IEN0.2 EX1 External interrupt 1 enable bit.
IEN0.1 ET0 Timer 0 interrupt enable bit.
IEN0.0 EX0 External interrupt 0 enable bit.
SU01454
ET0EX1ET1ES0ES1ECEA
01234567
Figure 35. IE Registers
