Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
76
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0 °C to +70 °C, 5 V ± 10% or –40 °C to +85 °C; 5V ±5%; V
SS
= 0 V
TEST
LIMITS
CONDITIONS
MIN TYP
1
MAX
V
IL
Input low voltage 4.5 V < V
CC
< 5.5 V –0.5 0.2 V
CC
–0.1 V
V
IL2
Input low voltage to P1.6/SCL, P1.7/SDA
11
–0.5 0.3V
DD
V
V
IH
Input high voltage (ports 0, 1, 2, 3, EA) 0.2V
CC
+0.9 V
CC
+0.5 V
V
IH1
Input high voltage, XTAL1, RST 0.7V
CC
V
CC
+0.5 V
V
IH2
Input high voltage, P1.6/SCL, P1.7/SDA
11
0.7V
DD
6.0 V
V
OL
Output low voltage, ports 1, 2, 3
8
V
CC
= 4.5 V
I
OL
= 1.6 mA
2
– 0.4 V
V
OL1
Output low voltage, port 0, ALE, PSEN
7,
8
V
CC
= 4.5 V
I
OL
= 3.2 mA
2
– 0.45 V
V
OL2
Output low voltage, P1.6/SCL, P1.7/SDA I
OL
= 3.0 mA – 0.4 V
V
OH
Output high voltage, ports 1, 2, 3
3
V
CC
= 4.5 V
I
OH
= –30 µA
V
CC
– 0.7 – V
V
OH1
Output high voltage (port 0 in external bus mode),
ALE
9
, PSEN
3
V
CC
= 4.5 V
I
OH
= –3.2 mA
V
CC
– 0.7 – V
I
IL
Logical 0 input current, ports 1, 2, 3 V
IN
= 0.4 V –1 –75 µA
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3
6
V
IN
= 2.0 V
See Note 4
– –650 µA
I
LI
Input leakage current, port 0 0.45 < V
IN
< V
CC
– 0.3 – ±10 µA
I
L2
Input leakage current, P1.6/SCL, P1.7/SDA
0V < VI < 6 V
0V < V
DD
< 5.5 V
– 10 µA
I
CC
Power supply current (see Figure 64): See Note 5
Active mode (see Note 5)
Idle mode (see Note 5)
Power-Down mode or clock stopped (see Figure 71
T
amb
= 0 °C to 70 °C 20 100 µA
for conditions)
T
amb
= –40 °C to +85 °C 125 µA
Programming and erase mode f
osc
= 20 MHz 60 mA
R
RST
Internal reset pull-down resistor 40 225 kΩ
C
IO
Pin capacitance
10
(except EA) – 15 pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
CC
–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2 V.
5. See Figures 68 through 71 for I
CC
test conditions and Figure 64 for I
CC
vs Freq.
Active mode: I
CC(MAX)
= (2.8 × FREQ. + 8.0)mA for all devices, in 6 clock mode; (1.4 × FREQ. + 8.0)mA in 12 clock mode.
Idle mode: I
CC(MAX)
= (1.2 × FREQ. +1.0)mA in 6 clock mode; (0.6 × FREQ. +1.0)mA in 12 clock mode.
6. This value applies to T
amb
= 0 °C to +70 °C.
7. Load capacitance for port 0, ALE, and PSEN
= 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 15 mA (*NOTE: This is 85 °C specification.)
Maximum I
OL
per 8-bit port: 26 mA
Maximum total I
OL
for all outputs: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA
is 25 pF).
11. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so an input voltage below 1.5 V will be recognized as a logic 0
while an input voltage above 3.0 V will be recognized as a logic 1.
