Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
52
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
765432 1 0
EXTRAM AO
AUXR.1 EXTRAM (See more detailed description in
AUXR.0 AO Figure 53.)
Dual DPTR
The dual DPTR structure (see Figure 39) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS (AUXR1.0), that allows the program
code to switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxxx0x0B
AUXR1 (A2H)
765 43210
ENBOOT GF2 0 DPS
Where:
DPS (AUXR1.0), enables switching between DPTR0 and DPTR1.
Select Reg DPS
DPTR0 0
DPTR1 1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
The ENBOOT bit determines whether the BOOTROM is enabled
or disabled. This bit will automatically be set if the status byte is
non zero during reset or PSEN
is pulled low, ALE floats high, and
EA > V
IH
on the falling edge of reset. Otherwise, this bit will be
cleared during reset.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 39.
DPTR Instructions
The instructions, that refer to DPTR, refer to the data pointer that is
currently selected by the DPS bit (AUXR1.0). The six instructions
that use the DPTR are as follows:
INC DPTR Increments the data pointer by 1
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR Move code byte relative to DPTR to ACC
MOVX A, @ DPTR Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
53
Programmable Counter Array (PCA)
The Programmable Counter Array available on the 89C66x is a
special 16-bit Timer that has five 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to
operate in one of four modes: rising and/or falling edge capture,
software timer, high-speed output, or pulse width modulator. Each
module has a pin associated with it in port 1. Module 0 is connected
to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The basic PCA
configuration is shown in Figure 40.
The PCA timer is a common time base for all five modules and can
be programmed to run at: 1/6 the oscillator frequency, 1/2 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin
(P1.2). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR as follows (see Figure 43):
CPS1 CPS0 PCA Timer Count Source
0 0 1/6 oscillator frequency (6 clock mode);
1/12 oscillator frequency (12 clock mode)
0 1 1/2 oscillator frequency (6 clock mode);
1/4 oscillator frequency (12 clock mode)
1 0 Timer 0 overflow
1 1 External Input at ECI pin
In the CMOD SFR, there are three additional bits associated with
the PCA. They are CIDL which allows the PCA to stop during idle
mode, WDTE which enables or disables the watchdog function on
module 4, and ECF which, when set, causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 41.
The watchdog timer function is implemented in module 4 (see
Figure 50).
The CCON SFR contains the run control bit for the PCA, and the
flags for the PCA timer (CF) and each module (refer to Figure 44).
To run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
also can only be cleared by software. The PCA interrupt system is
shown in Figure 42.
Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 45). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2), when set, causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module’s capture/compare register. The match bit
MAT (CCAPMn.3), when set, will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module’s capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the positive
edge. If both bits are set, both edges will be enabled and a capture
will occur for either transition. The last bit ECOM (CCAPMn.6), when
set, enables the comparator function. Figure 46 shows the CCAPMn
settings for the various PCA functions.
There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
MODULE FUNCTIONS:
16-BIT CAPTURE
16-BIT TIMER
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER (MODULE 4 ONLY)
MODULE 0
MODULE 1
MODULE 2
MODULE 3
MODULE 4
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P3.4/CEX3
P3.5/CEX4
16 BITS
PCA TIMER/COUNTER
TIME BASE FOR PCA MODULES
16 BITS
SU01416
Figure 40. Programmable Counter Array (PCA)
Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
54
CF CR CCF4 CCF3 CCF2 CCF1 CCF0––
CCON
(C0H)
CH CL
OVERFLOW
INTERRUPT
16–BIT UP COUNTER
IDLE
TO PCA
MODULES
CMOD
(C1H)
CIDL WDTE –– –– –– CPS1 CPS0 ECF
OSC/6 (6 CLOCK MODE)
OR
OSC/12 (12 CLOCK MODE)
TIMER 0 OVERFLOW
EXTERNAL INPUT
(P1.2/ECI)
DECODE
00
01
10
11
SU01256
OSC/2 (6 CLOCK MODE)
OR
OSC/4 (12 CLOCK MODE)
Figure 41. PCA Timer/Counter
MODULE 0
MODULE 1
MODULE 2
MODULE 3
MODULE 4
PCA TIMER/COUNTER
CF CR CCF4 CCF3 CCF2 CCF1 CCF0––
CMOD.0 ECF
CCAPMn.0 ECCFn
TO
INTERRUPT
PRIORITY
DECODER
CCON
(C0H)
IE.6
EC
IE.7
EA
SU01097
Figure 42. PCA Interrupt System

P89C662HBA/00,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 32KB FLASH 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union