©2011 Silicon Storage Technology, Inc. DS25034A 09/11
6
4 Mbit (x16) Multi-Purpose Flash
SST39WF400B
Data Sheet
Microchip Technology Company
Device Operation
Commands, which are used to initiate the memory operation functions of the device, are written to the
device using standard microprocessor write sequences. A command is written by asserting WE# low
while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39WF400B is controlled by CE# and OE#; both have to be low for the
system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is
consumed.
OE# is the output control and is used to gate data from the output pins. The data bus is in high imped-
ance state when either CE# or OE# is high. See Figure 5.
Word-Program Operation
The SST39WF400B is programmed on a word-by-word basis. The sector where the word exists must
be fully erased before programming.
Programming is accomplished in three steps:
1. Load the three-byte sequence for Software Data Protection.
2. Load word address and word data. During the Word-Program operation, the addresses
are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first.
3. Initiate the internal Program operation after the rising edge of the fourth WE# or CE#,
whichever occurs first. Once initiated, the Program operation will be completed within 40
µs. See Figures 6 and 7 for WE# and CE# controlled Program operation timing diagrams
and Figure 18 for flowcharts.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the inter-
nal Program operation, the host is free to perform additional tasks. Any commands issued during the
internal Program operation are ignored.
