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SI5351C-A-GMR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
Si5351A/B/C
Preliminary Rev. 0.95 13
3.4. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB
Layout Guide” for details. Note that spread spectrum is not available on clocks synchronized to PLLB or to the
VCXO.
The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise
between system performance and EMI compliance.
Figure 6. Available Spread Spectrum Profiles
3.5. Control Pins (OEB, SSEN)
The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.
3.5.1. Output Enable (OEB)
The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is
held low, and disabled when pulled high. When disabled, the output state is configurable as disabled high, disabled
low, or disabled in high-impedance.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before
going into a disabled state.
3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only
This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread
spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of
evaluating the effect of using spread spectrum clocks during EMI compliance testing.
f
c
Reduced
Amplitude
and EMI
Down Spread
f
c
Reduced
Amplitude
and EMI
Center Spread
f
c
No Spread
Spectrum
Center
Frequency
Amplitude
Si5351A/B/C
14 Preliminary Rev. 0.95
4. I
2
C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
I
2
C interface. The following is a list of the common features that are controllable through the I
2
C interface. A
summary of register functions is shown in Section 7.
Read Status Indicators
Loss of signal (LOS) for the CLKIN input
Loss of lock (LOL) for PLLA and PLLB
Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Enable/disable for each clock output
Invert/non-invert for each clock output
Output divider values (2
n
, n=1.. 7)
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
The I
2
C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
The I
2
C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
I
2
C specification.
Figure 7. I
2
C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
require more than one Si5351 on a single I
2
C bus.
Figure 8. Si5351 I
2
C Slave Address
Data is transferred MSB first in 8-bit words as specified by the I
2
C specification. A write command consists of a 7-
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
SCL
VDD
SDA
I
2
C Bus
INTR
A0
I
2
C Address Select:
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Si5351
>1k
>
1k
4.7 k
Slave Address
1 1 0 0 0 0 0/1
A0
0123456
Si5351A/B/C
Preliminary Rev. 0.95 15
Figure 9. I
2
C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10.
Figure 10. I
2
C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 7. The timing specifications and
timing diagram for the I
2
C bus is compatible with the I
2
C-Bus Standard. SDA timeout is supported for compatibility
with SMBus interfaces.
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Write Operation – Single Byte
S 0 A Reg Addr [7:0]Slv Addr [6:0] A Data [7:0] PA
Write Operation - Burst (Auto Address Increment)
Reg Addr +1
S 0 A Reg Addr [7:0]Slv Addr [6:0] A Data [7:0] A Data [7:0] PA
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Read Operation – Single Byte
S 0 A Reg Addr [7:0]Slv Addr [6:0] A P
Read Operation - Burst (Auto Address Increment)
Reg Addr +1
S 1 ASlv Addr [6:0] Data [7:0] PN
S 0 A Reg Addr [7:0]Slv Addr [6:0] A P
S 1 ASlv Addr [6:0] Data [7:0] A PNData [7:0]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72

SI5351C-A-GMR

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Clock Generators & Support Products
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