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SI5351C-A-GMR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
Si5351A/B/C
Preliminary Rev. 0.95 61
Reset value = 0000 0000
Reset value = 11xx xxxx
Register 177. PLL Reset
BitD7D6D5D4D3D2D1D0
Name
PLLB_RST PLLA_RST
Type
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7PLLB_RSTPLLB_Reset.
Writing a 1 to this bit will reset PLLB. This is a self clearing bit (Si5351A/C only).
6 Reserved Leave as default.
5PLLA_RSTPLLA_Reset.
Writing a 1 to this bit will reset PLLA. This is a self clearing bit.
4:0 Reserved Leave as default.
Register 183. Crystal Internal Load Capacitance
BitD7D6D5D4D3D2D1D0
Name
XTAL_CL[1:0]
Type
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:6 XTAL_CL[1:0] Crystal Load Capacitance Selection.
These 2 bits determine the internal load capacitance value for the crystal. See "3.1.1.
Crystal Inputs (XA, XB)" on page 11.
00: Reserved. Do not select this option.
01: Internal CL = 6 pF.
10: Internal CL = 8 pF.
11: Internal CL = 10 pF (default).
5:0 Reserved Leave as default.
Si5351A/B/C
62 Preliminary Rev. 0.95
9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP)
Table 10. Si5351A Pin Descriptions
Pin Name
Pin Number
Pin Type* Function
20-QFN 24-QSOP
XA 1 6 I Input pin for external crystal.
XB 2 7 I Input pin for external crystal.
CLK0 13 21 O Output clock 0.
CLK1 12 20 O Output clock 1.
CLK2 9 15 O Output clock 2.
CLK3 8 14 O Output clock 3.
CLK4 19 3 O Output clock 4.
CLK5 17 1 O Output clock 5.
CLK6 16 24 O Output clock 6.
CLK7 15 23 O Output clock 7.
A0 3 9 I I
2
C address bit.
SCL 4 10 I I
2
C bus serial clock input. Pull-up to VDD core with 1 k
SDA 5 11 I/O I
2
C bus serial data input. Pull-up to VDD core with 1 k
SSEN 6 12 I Spread spectrum enable. High = enabled, Low = disabled.
OEB 7 13 I Output driver enable. Low = enabled, High = disabled.
VDD 20 4 P Core voltage supply pin. See 6.2.
VDDOA 11 18 P Output voltage supply pin for CLK0 and CLK1. See 6.2.
VDDOB 10 16 P Output voltage supply pin for CLK2 and CLK3. See 6.2.
VDDOC 18 2 P Output voltage supply pin for CLK4 and CLK5. See 6.2.
VDDOD 14 22 P Output voltage supply pin for CLK6 and CLK7. See 6.2.
GND Center Pad 5, 8, 17, 19 P Ground. Use multiple vias to ensure a solid path to GND.
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
20
19
18
17
16
XA
XB
A0
SCL
SDA
OEB
CLK3
CLK2
VDDOB
SSEN
Si5351A 20-QFN
Top View
GND
PAD
CLK6
CLK5
VDDOC
CLK4
VDD
VDDOA
CLK1
CLK0
VDDOD
CLK7
2
1
4
3
6
5
8
7
10
9
12
11
23
24
21
22
19
20
17
18
15
16
13
14
Si5351A 24-QSOP
Top View
CLK7
CLK6
CLK0
VDD0D
GND
CLK1
GND
VDDOA
CLK2
VDD0B
OEB
CLK3
VDDOC
CLK5
VDD
CLK4
XA
GND
GND
XB
SCL
A0
SSEN
SDA
Si5351A/B/C
Preliminary Rev. 0.95 63
10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP)
Table 11. Si5351B Pin Descriptions
Pin Name
Pin Number
Pin Type* Function
20-QFN 24-QSOP
XA 1 6 I Input pin for external crystal
XB 2 7 I Input pin for external crystal
CLK0 13 21 O Output clock 0
CLK1 12 20 O Output clock 1
CLK2 9 15 O Output clock 2
CLK3 8 14 O Output clock 3
CLK4 19 3 O Output clock 4
CLK5 17 1 O Output clock 5
CLK6 16 24 O Output clock 6
CLK7 15 23 O Output clock 7
VC 3 9 I VCXO control voltage input
SCL 4 10 I I
2
C bus serial clock input. Pull-up to VDD core with 1 k
SDA 5 11 I/O I
2
C bus serial data input. Pull-up to VDD core with 1 k
SSEN 6 12 I Spread spectrum enable. High = enabled, Low = disabled.
OEB 7 13 I Output driver enable. Low = enabled, High = disabled.
VDD 20 4 P Core voltage supply pin
VDDOA 11 18 P Output voltage supply pin for CLK0 and CLK1. See 6.2
VDDOB 10 16 P Output voltage supply pin for CLK2 and CLK3. See 6.2
VDDOC 18 2 P Output voltage supply pin for CLK4 and CLK5. See 6.2
VDDOD 14 22 P Output voltage supply pin for CLK6 and CLK7. See 6.2
GND Center Pad 5, 8, 17, 19 P Ground
*Note: I = Input, O = Output, P = Power
*Note: Input pins are not internally pulled up.
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
20
19
18
17
16
XA
XB
VC
SCL
SDA
OEB
CLK3
CLK2
VDDOB
SSEN
Si5351B 20-QFN
Top View
GND
PAD
CLK6
CLK5
VDDOC
CLK4
VDD
VDDOA
CLK1
CLK0
VDDOD
CLK7
2
1
4
3
6
5
8
7
10
9
12
11
23
24
21
22
19
20
17
18
15
16
13
14
Si5351B 24-QSOP
Top View
VDDOC
CLK5
VDD
CLK4
XA
GND
GND
XB
SCL
VC
SSEN
SDA
CLK7
CLK6
CLK0
VDD0D
GND
CLK1
GND
VDDOA
CLK2
VDD0B
OEB
CLK3
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72

SI5351C-A-GMR

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Buy SI5351C-A-GMR
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products
Lifecycle:
New from this manufacturer.
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