Si5351A/B/C
4 Preliminary Rev. 0.95
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature T
A
40258C
Core Supply Voltage V
DD
3.0 3.3 3.60 V
2.25 2.5 2.75 V
Output Buffer Voltage V
DDOx
1.71 1.8 1.89 V
2.25 2.5 2.75 V
3.0 3.3 3.60 V
Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
VDD and VDDOx can be operated at independent voltages.
Power supply sequencing for VDD and VDDOx requires that both voltage rails are powered at the same time.
Table 2. DC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Core Supply Current I
DD
Enabled 3 outputs 22 35 mA
Enabled 8 outputs 27 45 mA
Power Down (PDN = V
DD
)— 20 µA
Output Buffer Supply Current
(Per Output)*
I
DDOx
C
L
=5pF 2.2 5 mA
Input Current
I
CLKIN
CLKIN, SDA, SCL
Vin < 3.6 V
——10 µA
I
VC
VC 30 µA
Output Impedance Z
O
8 mA output drive current.
See "6. Design Consider-
ations" on page 21.
—85
*Note: Output clocks less than or equal to 100 MHz.
Si5351A/B/C
Preliminary Rev. 0.95 5
Table 3. AC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Power-up Time T
RDY
From V
DD
=V
DDmin
to valid
output clock, C
L
=5pF,
f
CLKn
>1MHz
—110ms
Output Enable Time T
OE
From OEB pulled low to valid
clock output, C
L
=5pF,
f
CLKn
>1MHz
——10 µs
Output Phase Offset P
STEP
333 ps/step
Spread Spectrum Frequency
Deviation
SS
DEV
Down spread –0.1 –2.5 %
Center spread ±0.1 ±1.5 %
Spread Spectrum Modulation
Rate
SS
MOD
30 31.5 33 kHz
VCXO Specifications (Si5351B only)
VCXO Control Voltage Range Vc 0 V
DD
/2 V
DD
V
VCXO Gain (configurable) Kv Vc = 10–90% of V
DD
, V
DD
= 3.3 V 18 150 ppm/V
VCXO Control Voltage Linearity KVL Vc = 10–90% of V
DD
–5 +5 %
VCXO Pull Range
(configurable)
PR V
DD
= 3.3 V* ±30 0 ±240 ppm
VCXO Modulation Bandwidth 10 kHz
*Note: Contact Silicon Labs for 2.5 V VCXO operation.
Table 4. Input Clock Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
CLKIN Input Low Voltage V
IL
–0.1 0.3 x V
DD
V
CLKIN Input High Voltage V
IH
0.7 x V
DD
—3.60 V
CLKIN Frequency Range f
CLKIN
10 100 MHz
Si5351A/B/C
6 Preliminary Rev. 0.95
Table 5. Output Clock Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
=–40 to 8C)
Parameter Symbol Test Condition Min Typ Max Units
Frequency Range F
CLK
0.008 160 MHz
Load Capacitance C
L
—515pF
Duty Cycle DC
Measured at V
DD
/2,
f
CLK
=50MHz
45 50 55 %
Rise/Fall Time
t
r
20%–80%, C
L
=5pF,
Drive Strength = 8 mA
0.5 1 1.5 ns
t
f
0.5 1 1.5 ns
Output High Voltage V
OH
C
L
=5pF
V
DD
– 0.6 V
Output Low Voltage V
OL
——0.6V
Period Jitter J
PER
Measured over 10k cycles
35 100 ps pk-pk
Period Jitter VCXO J
PER_VCXO
60 110 ps pk-pk
Cycle-to-Cycle Jitter J
CC
Measured over 10k cycles
—3090ps pk
Cycle-to-Cycle Jitter
VCXO
J
CC_VCXO
—5095ps pk
RMS Phase Jitter J
RMS
12 kHz–20 MHz
3.5 11 ps rms
RMS Phase Jitter VCXO J
RMS_VCXO
8.5 18.5 ps rms
Table 6. Crystal Requirements
1,2
Parameter
Symbol Min Typ Max Unit
Crystal Frequency f
XTAL
25 27 MHz
Load Capacitance C
L
6—12pF
Equivalent Series Resistance r
ESR
——150
Crystal Max Drive Level d
L
——100µW
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors.
2. Refer to “AN551: Crystal Selection Guide” for more details.

SI5351C-A-GMR

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Silicon Labs
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Clock Generators & Support Products
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