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SI5351C-A-GMR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
Si5351A/B/C
Preliminary Rev. 0.95 25
8. Register Descriptions
Reset value = 0000 0000
Register 0. Device Status
BitD7D6D5D4D3D2D1D0
Name
SYS_INIT LOL_B LOL_A LOS REVID[1:0]
Type
RRRRRR R
Bit Name Function
7SYS_INITSystem Initialization Status.
During power up the device copies the content of the NVM into RAM and performs a system
initialization. The device is not operational until initialization is complete. It is not recom-
mended to read or write registers in RAM through the I
2
C interface until initialization is com-
plete. An interrupt will be triggered (INTR pin = 0, Si5351C only) during the system
initialization period.
0: System initialization is complete. Device is ready.
1: Device is in system initialization mode.
6LOL_BPLLB Loss Of Lock Status.
Si5351A/C only. PLLB will operate in a locked state when it has a valid reference from CLKIN
or XTAL. A loss of lock will occur if the frequency of the reference clock forces the PLL to
operate outside of its lock range as specified in Table 3, or if the reference clock fails to meet
the minimum requirements of a valid input signal as specified in Table 4. An interrupt will be
triggered (INTR pin = 0, Si5351C) during a LOL condition.
0: PLL B is locked.
1: PLL B is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
5LOL_APLL A Loss Of Lock Status.
PLL A will operate in a locked state when it has a valid reference from CLKIN or XTAL. A loss
of lock will occur if the frequency of the reference clock forces the PLL to operate outside of
its lock range as specified in Table 3, or if the reference clock fails to meet the minimum
requirements of a valid input signal as specified in Table 4. An interrupt will be triggered
(INTR pin = 0, Si5351C only) during a LOL condition.
0: PLL A is operating normally.
1: PLL A is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
4LOSCLKIN Loss Of Signal (Si5351C Only).
A loss of signal status indicates if the reference clock fails to meet the minimum requirements
of a valid input signal as specified in Table 4. An interrupt will be triggered (INTR pin = 0,
Si5351C only) during a LOS condition.
0: Valid clock signal at the CLKIN pin.
1: Loss of signal detected at the CLKIN pin.
3:2 Reserved Leave as default.
1:0 REVID[1:0] Revision ID. Device revision number. Set at the factory.
Si5351A/B/C
26 Preliminary Rev. 0.95
Reset value = 0000 0000
Register 1. Interrupt Status Sticky
Bit D7 D6 D5 D4 D3D2D1D0
Name
SYS_INIT_STKY LOL_B_STKY LOL_A_STKY LOS_STKY
Type
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 SYS_INIT_STKY System Calibration Status Sticky Bit.
The SYS_INIT_STKY bit is triggered when the SYS_INIT bit (register 0, bit 7) is trig-
gered high. It remains high until cleared. Writing a 0 to this register bit will cause it to
clear.
0: No SYS_INIT interrupt has occurred since it was last cleared.
1: A SYS_INIT interrupt has occurred since it was last cleared.
6 LOL_B_STKY PLLB Loss Of Lock Status Sticky Bit.
The LOL_B_STKY bit is triggered when the LOL_B bit (register 0, bit 6) is triggered
high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No PLL B interrupt has occurred since it was last cleared.
1: A PLL B interrupt has occurred since it was last cleared.
5 LOL_A_STKY PLLA Loss Of Lock Status Sticky Bit.
The LOL_A_STKY bit is triggered when the LOL_A bit (register 0, bit 5) is triggered
high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No PLLA interrupt has occurred since it was last cleared.
1: A PLLA interrupt has occurred since it was last cleared.
4LOS_STKYCLKIN Loss Of Signal Sticky Bit (Si5351C Only).
The LOS_STKY bit is triggered when the LOS bit (register 0, bit 4) is triggered high. It
remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No LOS interrupt has occurred since it was last cleared.
1: A LOS interrupt has occurred since it was last cleared.
3:0 Reserved Leave as default.
Si5351A/B/C
Preliminary Rev. 0.95 27
Reset value = 0000 0000
Register 2. Interrupt Status Mask
Bit D7 D6 D5 D4 D3D2D1D0
Name
SYS_INIT_MASK LOL_B_MASK LOL_A_MASK LOS_MASK
Type
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 SYS_INIT_MASK System Initialization Status Mask.
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when
SYS_INIT is asserted.
0: Do not mask the SYS_INIT interrupt.
1: Mask the SYS_INIT interrupt.
6 LOL_B_MASK PLLB Loss Of Lock Status Mask.
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOL_B
is asserted.
0: Do not mask the LOL_B interrupt.
1: Mask the LOL_B interrupt.
5 LOL_A_MASK PLL A Loss Of Lock Status Mask.
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOL_A
is asserted.
0: Do not mask the LOL_A interrupt.
1: Mask the LOL_A interrupt.
4 LOS_MASK CLKIN Loss Of Signal Mask (Si5351C Only).
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOS is
asserted.
0: Do not mask the LOS interrupt.
1: Mask the LOS interrupt.
3:0 Reserved Leave as default.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72

SI5351C-A-GMR

Mfr. #:
Buy SI5351C-A-GMR
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products
Lifecycle:
New from this manufacturer.
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