Si5351A/B/C
Preliminary Rev. 0.95 7
Table 7. I
2
C Specifications (SCL,SDA)
1
Parameter
Symbol Test Condition Standard Mode
100 kbps
Fast Mode
400 kbps
Unit
Min Max Min Max
LOW Level
Input Voltage
V
ILI2C
–0.5
0.3 x V
DDI2
C
–0.5 0.3 x V
DDI2C
2
V
HIGH Level
Input Voltage
V
IHI2C
0.7 x V
DDI2
C
3.63 0.7 x V
DDI2C
2
3.63 V
Hysteresis of
Schmitt Trigger
Inputs
V
HYS
—— 0.1 V
LOW Level
Output Voltage
(open drain or
open collector)
at 3 mA Sink
Current
V
OLI2C
2
V
DDI2C
2
= 2.5/3.3 V 0 0.4 0 0.4 V
V
DDI2C
2
= 1.8 V 0 0.2 x V
DDI2C
V
Input Current I
II2C
–10 10 –10 10 µA
Capacitance for
Each I/O Pin
C
II2C
V
IN
= –0.1 to V
DDI2C
—4 4pF
I
2
C Bus
Timeout
T
TO
Timeout Enabled 25 35 25 35 ms
Notes:
1. Refer to NXP’s UM10204 I
2
C-bus specification and user manual, revision 03, for further details, go to:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. Only I
2
C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
Table 8. Thermal Characteristics
Parameter Symbol Test Condition Package Value Unit
Thermal Resistance
Junction to Ambient
JA
Still Air
10-MSOP 131 °C/W
24-QSOP 80 °C/W
20-QFN 51 °C/W
Thermal Resistance
Junction to Case
JC
Still Air
10-MSOP 43 °C/W
24-QSOP 31 °C/W
20-QFN 16 °C/W
Si5351A/B/C
8 Preliminary Rev. 0.95
Table 9. Absolute Maximum Ratings
1
Parameter Symbol Test Condition Value Unit
DC Supply Voltage V
DD_max
–0.5 to 3.8 V
Input Voltage
V
IN_CLKIN
CLKIN, SCL, SDA –0.5 to 3.8 V
V
IN_VC
VC –0.5 to (VDD+0.3) V
V
IN_XA/B
Pins XA, XB –0.5 to 1.3 V V
Junction Temperature T
J
–55 to 150 °C
Soldering Temperature (Pb-free
profile)
2
T
PEAK
260 °C
Soldering Temperature Time at
TPEAK (Pb-free profile)
2
T
P
20–40 Sec
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
Si5351A/B/C
Preliminary Rev. 0.95 9
2. Detailed Block Diagrams
Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices
PLL
B
PLL
A
SDA
SCL
OSC
XA
XB
VDDO
R0
R1
CLK0
CLK1
R2
CLK2
MultiSynth
0
MultiSynth
1
MultiSynth
2
VDD
GND
10-MSOP
Si5351A 3-Output
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSynth
0
MultiSynth
1
MultiSynth
2
MultiSynth
3
MultiSynth
4
MultiSynth
5
MultiSynth
6
MultiSynth
7
VDD
GND
20-QFN, 24-QSOP
SCL
A0
SDA
Control
Logic
OEB
SSEN
I
2
C
Interface
Si5351A 8-Output
I
2
C
Interface
PLL
B
PLL
A
OSC
XA
XB

SI5351C-A-GMR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union