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SSTUB32S868DHLF
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
10
ICSSSTUB32S868D
Advance Information
08/14/06
Parity Logic Diagram
D
CK
R
M2
RST#
M1
CK#
L1
CK
22
22
D1-D12,
D17-D20,
D22,
D24-D2
8
22
A5, AB5
V
REF
CE
Q1A-Q12A,
Q17A-Q20A ,
Q22A,
Q24A-Q2
8
A
22
22
D
Q
R
P
AR_IN
CE
L3
QERR#
M3
D
CK
R
N2
QCS0A#
N1
DCS0#
M7
QCS0B#
L2
CSGEN
D
CK
R
P1
DCS1#
P2
QCS1A#
M
8
QCS1B#
Parity Generator
and
Error Check
22
D1-D12,
D17-D20, D22,
D24-D2
8
D1-D12,
D17-D20, D22,
D24-D2
8
D1-D12,
D17-D20, D22,
D24-D2
8
Q1B-Q12B,
Q17B-Q20B ,
Q22B,
Q24B-Q2
8
B
Q
CK
Q
Q
Register B configuration with C= 1; (positive logic)
11
ICSSSTUB32S868D
Advance Information
08/14/06
Register Timing
CK
Dn,
DODTn,
DCKEn
RST#
t
su
t
h
t
su
t
h
t
pdm
,t
pdmss
CK to Q
CSGEN
CK#
Qn, QODTn,
QCKEn
P
AR_IN
nn
+
1
n
+ 2
n + 3
n
+ 4
t
PHL
CK to QERR#
QERR#
t
PHL
, t
PLH
CK to QERR#
t
act
H, L, or X
H or L
DCS0#
DCS1#
Data to QERR# Latency
†
After RESET# is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of ta
ct max,
to avoid false error.
If the data is clocked in on the n clock pulse, the QERR# output sognal will be produced on the n+2 clock pulse and it will be
valid on the
n+3 clock pulse.
‡
12
ICSSSTUB32S868D
Advance Information
08/14/06
Register Timing
†
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n + 2 clock pulse and it will
be valid on
the n + 3 clock pulse. If an error occurs and the QERR# output is driven low, it stays low for a minimum of two clock cycles or
until
RST# is driven low.
CK
Dn, DODTn,
DCKEn
RST#
t
su
t
h
t
su
t
h
t
pdm
,t
pdmss
CK to Q
CSGEN
DCS0#
CK#
Qn, QODTn,
QCKEn
P
AR_IN
nn
+
1
n
+ 2
n + 3
n
+ 4
QERR#
t
PHL
or t
PLH
CK to QERR#
Unknown input
event
H or L
Output signal is dependent on
the prior unknown input
event
DCS1#
Data to QERR# Latency
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
SSTUB32S868DHLF
Mfr. #:
Buy SSTUB32S868DHLF
Manufacturer:
IDT
Description:
Buffers & Line Drivers 28-Bit Configurable Registered Buffer for DDR2
Lifecycle:
New from this manufacturer.
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