16
ICSSSTUB32S868D
Advance Information
08/14/06
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol Parameter
Measurement
Conditions
MIN MAX Units
fmax Max input clock frequency 410 MHz
t
PDM
Propagation delay, single
bit switching
CK to CK#Qn 1.2 1.9 ns
t
LH
Low to High propagation
delay
CK to CK#to QERR# 1.2 3 ns
t
HL
High to low propagation
delay
CK to CK#to QERR# 1 2.4 ns
t
PDMSS
Propagation delay
simultaneous switching
CK to CK#Qn 2 ns
t
PHL
High to low propagation
delay
Reset# to Qn 3ns
t
PLH
Low to High propagation
delay
Reset# to QERR# 3ns
1. Guaranteed by design, not 100% tested in production.
(over recommended operating free-air temperature range, unless otherwise noted)
Timing Requirements
NOTE 1 This parameter is not necessarily production tested.
NOTE 2
V
REF
must be held at a valid input voltage level and data inputs must be held low for a minimum time of
t
ACT
(max) after RESET# is taken high.
NOTE 3
V
REF
, Data and clock inputs must be held at valid voltage levels (not floating) a minimum time of t
INACT
(max) after RESET# is taken low.
Symbol Parameter Min Max Unit
f
clock
Clock frequency
- 410 MHz
t
W
Pulse duration, CK, CK# HIGH or LOW
1-ns
t
ACT
Differential inputs active time (See Notes 1 and 2)
-10ns
t
INACT
Differential inputs inactive time (See Notes 1 and 3)
-15ns
t
SU
Setup time
DCS before CK , CK# , CSR# high;
CSR# before CK , CK# , DCS# high
0.7 - ns
Setup time
DCS# before CK , CK# , CSR# low
0.5 - ns
Setup time
DODT, DCKE and data before CK , CK
# 0.5 - ns
Setup time
PAR_IN before CK , CK#
0.5 - ns
t
H
Hold time
DCS#, DODT, DCKE and data after CK , CK
# 0.6 - ns
Hold time
PAR_IN after CK , CK#
0.5 - ns
17
ICSSSTUB32S868D
Advance Information
08/14/06
Notes: 1. C
L
incluces probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DD
or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR 10 MHz,
Zo=50, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V
REF
= V
DD
/2
6. V
IH
= V
REF
+ 250 mV (ac voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS input.
7. V
IL
= V
REF
- 250 mV (ac voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
8. V
ID
= 600 mV
9. t
PLH
and t
PHL
are the same as t
PDM
.
Figure 6 Parameter M easurement I nfor mation (V
DD
= 1.8 V ± 0.1 V)
R
L
= 1000
C
L
= 30 pF
(see Note 1)
LOAD CIRCUI
T
t
w
V
ICR
V
ICR
Inpu t
V
IH
V
IL
VOLTAGE WAVEFORMS – PULSE DURATION
V
REF
V
REF
Inpu t
t
su
t
h
V
ID
V
ICR
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
V
ICR
V
ID
V
ICR
Output
V
OL
V
OH
V
TT
V
TT
t
PHL
t
PLH
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
t
RPHL
V
OL
V
OH
V
IL
V
IH
Output
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
V
DD
/2
V
TT
t
act
t
inact
LV CMOS
Input
RST#
VOLTAGE AND CURRENT WAVEFORM
S
I
DD
(see
Note 2)
90%
10%
INPUTS ACTIVE AND INACTIVE TIME
S
0 V
V
DD
Tes t Po i n t
V
DD
/2 V
DD
/2
VCMOS
Inp ut
RS
T#
TL=350ps, 50
DUT
CK#
Ou
t
TL=50
CK Inpu
ts
V
ID
CK#
CK
CK#
CK
R
L
= 100
CK
Tes t Po i n t
Tes t Po i n t
R
L
= 1000
V
DD
18
ICSSSTUB32S868D
Advance Information
08/14/06
Output slew rate measurement information (V
DD
=1.8V±0.1V)
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z
o
=50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) C
L
includes probe and jig capacitance.
Figure 12 — Load circuit, HIGH-to-LOW slew measurement
Figure 13 — Voltage waveforms, HIGH-to-LOW slew rate measurement
(1) C
L
includes probe and jig capacitance.
Figure 14 Load circuit, LOW-to-HIGH slew measurement
Figure 15 — Voltage waveforms, LOW-to-HIGH slew rate measurement
C
L
= 10 pF
SEE NOTE (1)
V
DD
OUT
DUT
TEST POINT
R
L
= 50
002aaa377
V
OH
V
OL
OUTPUT
80%
20%
dv_f
dt_f
002aaa378
C
L
= 10 pF
SEE NOTE (1)
OUT
DUT
TEST POINT
R
L
= 50
002aaa379
V
OH
V
OL
80%
20%
dv_r
dt_r
OUTPUT
002aaa380

SSTUB32S868DHLF

Mfr. #:
Manufacturer:
IDT
Description:
Buffers & Line Drivers 28-Bit Configurable Registered Buffer for DDR2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet