SSTUB32S868DHLF Datasheet SSTUB32S868DHLF | P4-P6

ICSSSTUB32S868D

Advance Information

08/14/06

General Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All inputs are compatible

with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET)

inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet

SSTL_18 specifications, except the open-drain error (QERR) output.

The ICSSSTUB32S868D operates from a differential clock (CK and CK). Data are registered at the crossing of CK

going high and CK going low. The device supports low-power standby operation. When RESET is low, the differential

input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In

addition, when RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET

and C inputs always must be held at a valid logic high or low level. To ensure defined outputs from the register before

a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM

application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing

relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs

will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of

reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as

the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input

receivers are fully enabled, the design of the ICSSSTUB32S868D must ensure that the outputs will remain low, thus

ensuring no glitches on the output.

Inputs Output

RST# DCS0# DCS1# CK CK#

Σ of inputs = H

(D1 - D28)

PAR_I N

†

QERR#

‡

Even L H

Odd L L

HLX Even H L

Odd H H

Even L H

H X L Odd L L

Even H L

Odd H H

QERR#

HXXL or HL or H X X

QERR#

X or

floating

X or

floating

X or

floating

X or

floating

X or

floating

↑

↓

† PAR_IN arrives one clock cycle after the data to which it applies.

‡ This transition assumes QERR# is high at the crossing of CK going high and CK#

going low. If QERR# is low, it stays latches low for two clock cycles or until RST#

is driven low.

If DCS0#, DCS1#, and CSGEN are driven high, the device is placed in low-power mode

(LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the

QERR# output is driven low, it stays latches low for the LPM duration plus two clock cycles

or until RST# is driven low.

ICSSSTUB32S868D

Advance Information

08/14/06

The ICSSSTUB32S868D includes a parity checking function. Parity, which arrives one cycle after the data input to which

it applies, is checked on the PAR_IN input of the device. The corresponding QERR output signal for the data inputs

is generated two clock cycles after the data, to which the QERR signal applies, is registered. The ICSSSTUB32S868D

accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on

the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when

C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is

even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined

with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. If an

error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET

is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock

duration equal to the parity error duration or until RESET is driven low. If a parity error occurs on the clock cycle before

the device enters the low-power (LPM) and the QERR output is driven low, then it stays lateched low for the LPM duration

plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1,

DCS0 and DCS1) are not included in the parity check computation.

The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration (when

high). The C input should not be switched during normal operation. It should be hardwired to a valid low or high level

to configure the register in the desired mode. The device also supports low-power active operation by monitoring both

system chip select (DCS0 and DCS1) and CSGEN inputs and will gate the Qn outputs from changing states when

CSGEN, DCS0, and DCS1 inputs are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs will function normally.

Also, if both DCS0 and DCS1 inputs are high, the device will gate the QERR output from changing states. If either DCS0

or DCS1 is low, the QERR output will function normally. The RESET input has priority over the DCS0 and DCS1 control

and when driven low will force the Qn outputs low, and the QERR output high. If the chip-select control functionality

is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0

and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and DCS1 only,

then the CSGEN input should be pulled up to VDD through a pullup resistor. The two VREF pins (A1 and V1) are

connected together internally by approximately 150 .. However, it is necessary to connect only one of the two VREF

pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.

General Description (Continued)

ICSSSTUB32S868D

Advance Information

08/14/06

Ball Assignment

†

Data inputs = D1-D5, D7, D9-D12, D17-D28 when C=0

Data inputs = D1-D12, D17-D20, D22, D24-D28 when C=1

Data outputs = Q1-Q5, Q7, Q9-Q12, Q17-Q28 when C=0

Data outputs = Q1-Q12, Q17-Q20, Q22, Q24-Q28 when C=1

‡

Terminal

name

Description

Electrical

characteristics

GND

Ground Ground input

Power supply voltage 1.8-V nominal

REF

Input reference voltage 0.9-V nominal

Positive master clock input Differential input

Differential input

CK#

Negative master clock input

Configuration control inputs - Register A or Register B

RST#

Asynchronous reset input – resets registers and disables VREF data

and clock differential-input receivers

CSGEN

Chip select gate enable – When high, D1-D28† inputs will be latched only

when at least one chip select input is low during the rising edge of the clock. When

low, theD1-D28† inputs will be latched and redriven on every rising edge of the clock.

LVCMOS input

LVCMOS inputs

D1-D28

†

Data input – clocked in on the crossing of the rising edge of CK and

the falling edge of CK#.

SSTL_18 input

DCS0#,

DCS1#

Chip select inputs – These pins initiate DRAM address/command decodes,

and as such at least one will be low when a valid address/command is

present. The Register can be programmed to redrive all D inputs

(CSGEN high) only when atleast one chip select input is low. If CSGEN,

DCS0#, and DCS1# inputs are high, D1–D28† inputs will be disabled.

SSTL_18 input

DODT0,

DODT1

The outputs of this register bit will not be suspended by the DC0# and

DCS1# control.

DCKE0,

DCKE1

The outputs of this register bit will not be suspended by the DC0# and

DCS1# control.

PAR_I N

Parity input - arrives one clock cycle after the corresponding data input.

Q1-Q28‡

Data outputs that are suspended by the DC0# and DCS1# control. 1.8-V CMOS outputs

QCS0#, QCS1#

Data output that will not be suspended by the DC0# and DCS1# control. 1.8-V CMOS output

QODT0,

QODT1

Data output that will not be suspended by the DC0# and DCS1# control. 1.8-V CMOS output

QCKE0,

QCKE1

Data output that will not be suspended by the DC0# and DCS1# control. 1.8-V CMOS output

QERR# Output error bit - generated one clock cycle after the corresponding data output Open-drain output

No internal connection

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SSTUB32S868DHLF

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Buffers & Line Drivers 28-Bit Configurable Registered Buffer for DDR2

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