7
ICSSSTUB32S868D
Advance Information
08/14/06
Block Diagram
D
CK
R
To 21 Other Channels
(D2-D5, D7, D9-D12, D17-D28)
M2
F2, E2
RST#
QCKE0A,
QCKE1A
M1
CK#
L1
CK
A5, AB5
V
REF
D1, C1
DCKE0,
DCKE1
H8, F8
QCKE0B,
QCKE1B
D
CK
R
N2, P2
QODT0A,
QODT1A
N1, P1
DODT0,
DODT1
M7, M8
QODT0B,
QODT1B
D
CK
R
K2
QCS0A#
K1
DCS0#
L7
QCS0B#
L2
CSGEN
A2
D1
D
CK
R
A7
Q1A
A8
Q1B
D
CK
R
One of 22 Channels
CE
2
2
2
2
2
2
2
2
J1
DCS1#
J2
QCS1A#
L8
QCS1B#
2
2
Q
Q
Q
Q
Q
Register A configuration with C= O; (positive logic)
8
ICSSSTUB32S868D
Advance Information
08/14/06
Parity Logic Diagram
D
CK
R
M2
RST#
M1
CK#
L1
CK
22
22
D1-D5,
D7,
D9-D12,
D17-D28
22
A5, AB5
V
REF
CE
Q1A-Q5A,
Q7A,
Q9A-Q12A,
Q17A-Q28A
22
22
D
Q
R
PAR_IN
CE
L3
QERR#
M3
D
CK
R
K2
QCS0A#
K1
DCS0#
L7
QCS0B#
L2
CSGEN
D
CK
R
J1
DCS1#
J2
QCS1A#
L8
QCS1B#
Parity Generator
and
Error Check
22
D1-D5, D7,
D9-D12,
D17-D28
D1-D5, D7,
D9-D12,
D17-D28
D1-D5, D7,
D9-D12,
D17-D28
Q1B-Q5B,
Q7B,
Q9B-Q12B,
Q17B-Q28B
Q
CK
Q
Q
Register A configuration with C= O; (positive logic)
9
ICSSSTUB32S868D
Advance Information
08/14/06
Block Diagram
D
CK
R
To 21 Other Channels
(D2-D12, D17-D20, D22, D24-D28)
M2
U2, V2
RST#
QCKE0A,
QCKE1A
M1
CK#
L1
CK
A5, AB5
V
REF
W1, Y1
DCKE0,
DCKE1
R8, U8
QCKE0B,
QCKE1B
D
CK
R
K2, J2
QODT0A,
QODT1A
K1, J1
DODT0,
DODT1
L7, L8
QODT0B,
QODT1B
D
CK
R
N2
QCS0A#
N1
DCS0#
M7
QCS0B#
L2
CSGEN
A2
D1
D
CK
R
A7
Q1A
A8
Q1B
D
CK
R
One of 22 Channels
CE
2
2
2
2
2
2
2
2
P1
DCS1#
P2
QCS1A#
M8
QCS1B#
2
2
Q
Q
Q
Q
Q
Register B configuration with C= 1; (positive logic)

SSTUB32S868DHLF

Mfr. #:
Manufacturer:
IDT
Description:
Buffers & Line Drivers 28-Bit Configurable Registered Buffer for DDR2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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