DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
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Data Valid
With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (t
HD:DAT
after the falling edge of SCL and t
SU:DAT
before the rising edge of SCL, see Figure 6).
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
t
SU:DAT
+ t
R
in Figure 6) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledged by Slave
Usually, a slave device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. The
master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges must
pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH period
of the acknowledge-related clock pulse plus the required setup and hold time (t
HD:DAT
after the falling edge of SCL
and t
SU:DAT
before the rising edge of SCL).
Acknowledged by Master
To continue reading from a slave, the master is obliged to generate an acknowledge after the receipt of each byte.
The master must generate the clock pulse for each acknowledge bit and, during the acknowledge clock pulse, pull
SDA LOW in such a way that SDA is stable LOW during the HIGH period of the acknowledge-related clock pulse.
The setup and hold time (t
HD:DAT
after the falling edge of SCL and t
SU:DAT
before the rising edge of SCL) also apply
to the master.
Not Acknowledged by Slave
A slave device may be unable to receive or transmit data, e.g., because it is busy. In SMBus mode, the DS28CZ04
will always acknowledge its slave address. However, some time later the device may refuse to accept data, e.g.,
because of an invalid access mode or an EEPROM write cycle in progress. In this case the DS28CZ04 will not
acknowledge any of the bytes that it refuses and will leave SDA HIGH during the HIGH period of the acknowledge-
related clock pulse. See section Read and Write for a detailed list of situations where the DS28CZ04 does not
acknowledge.
Not Acknowledged by Master
At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the
master does not acknowledge the last byte that it has received from the slave. In response, the slave releases
SDA, allowing the master to generate the STOP condition.
Figure 6. I²C/SMBus Timing Diagram
SCL
SDA
STOP START
t
BUF
t
HD:STA
t
LOW
t
R
t
HD:DAT
t
HIGH
t
SU:DAT
Repeated
START
t
SU:STA
t
F
t
HD:STA
t
SP
t
SU:STO
Spike
Suppression
NOTE: Timing is referenced to V
ILMAX
and V
IHMIN
.
